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Re-Entrant ISRs in C

Anthony F. Seely
Guru 69070 points

Other Parts Discussed in Thread: HALCOGEN

The ARM Compiler manual states

"Interrupt routines are not reentrant. If an interrupt routine enables interrupts of its type, it must save a
copy of the return address and SPSR (the saved program status register) before doing so."

Is there an example of how this can be implemented using a C interrupt service routine that is marked with the #pragma INTERRUPT?

We are considering the addition of inline assembly to save the extra registers that are not saved by #pragma INTERRUPT; but I've been told that the final ordering of inline assembly code versus compiler generate instructions may not be the same order as it appears in the C source.   So concerned about adding inline asm() statements to handle this critical job.

If there's no safe way to 'augment' the #pragma INTERRUPT  routine written in C, would it be possible to add a #pragma REENTRANT_INTERRUPT in some future version of the compiler?

  • Prodigy 80 points

    I have learned that there is an enhancement request ticket in to the compiler team, SDSCM00045251.  But no commitment on when/how to implement the enhancement.

    Is there any way I can know (or be notified) when this enhancement is made or if the request has been rejected?

    Thanks!

  • in reply to David Barnard
    TI__Guru**** 253380 points

    You can track this issue with the SDOWP link below in my signature.

    Thanks and regards,

    -George

  • Prodigy 10 points

    Below is what we are currently doing to handle reentrant interrupts using Halcogen, CCS 5, and an RM48.  This work originated from the following sources:

    1)      http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbeacfi.html

    2)      http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/164944.aspx

    Even though the RM48 utilizes an  ARM Cortex R4 (ARMv7-R) the example provided for the ARMv4/v5TE seems to work using a reduces instruction set (no SRSDB/CPS instructions as in the ARMv6 example). 

    Please provide feedback using the example below to ensure we are performing the correct steps to allow reentrant interrupts within a C context (we would prefer not to use an assembly file for future maintenance and support).     

    /* USER CODE BEGIN (73) */
    /* USER CODE END */
     
    /** @fn void rtiCompare0Interrupt(void)
    *   @brief RTI1 Compare 0 Interrupt Handler
    *
    *   RTI1 Compare 0 interrupt handler
    *
    */
    #pragma CODE_STATE(rtiCompare0Interrupt, 32)
    #pragma INTERRUPT(rtiCompare0Interrupt, IRQ)
     
    void rtiCompare0Interrupt(void)
    {
           /* USER CODE BEGIN (74) */
           asm("   PUSH {LR}                 ; Push the lr_irq");
           asm("   MRS LR, SPSR       ; Copy SPSR_IRQ to LR");
           asm("   PUSH {R0-R4,R12,LR} ; Push APPCS regs and SPSR_IRQ");
           rtiREG1->INTFLAG = 1U;
           asm("   MSR CPSR_c, #0x9F   ; switch to SYS mode. USR mode registers are now current");
           asm("   AND R1, SP, #4     ; test alignment of the stack");
           asm("   SUB SP, SP, R1     ; remove any misalignment (0 or 4)");
           asm("   PUSH {R1,LR}       ; store the adjustment and lr_USR");
           _enable_IRQ();
           rtiNotification(rtiNOTIFICATION_COMPARE0);
           _disable_IRQ();
           asm("   POP {R1,LR}               ; restore stack adjustment and lr_USR");
           asm("   ADD SP, SP, R1      ; add the stack adjustment (0 or 4)");
           asm("   MSR CPSR_c, #0x92   ; switch to IRQ mode and keep IRQ disabled. FIQ is still enabled.");
           asm("   POP {R0-R4,R12,LR}  ; restore registers and");
           asm("   MSR SPSR_cxsf, LR   ; spsr_IRQ");
           asm("   POP {LR}            ; restore lr_irq");
           /* USER CODE END */
    #if 0
           rtiREG1->INTFLAG = 1U;
           rtiNotification(rtiNOTIFICATION_COMPARE0);
     
           /* USER CODE BEGIN (75) */
    #endif
           /* USER CODE END */
    }

  • in reply to Kerry Grand
    Prodigy 80 points

    As Kerry requested, could someone from TI review this code?  Without a #pragma REENTRANT_INTERRUPT we have been told assembly is the only approach.  The OP, Anthony, started this thread for Kerry and I.  Since it doesn't sound like the enhancement request will happen soon, we really need some confidence in what we are doing regarding reentrant interrupts.

    Thanks!