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ARM cortex m4 compiler questions

Eric Zhang16395
Intellectual 795 points

Hi Compiler team,

  We have been using CL470 to compile cortex M4F. We leveraged quite a bit sample code from stellaris team. I looks to me that the sample code does not context stacking R4-R11 (it relys on the M4 hardware to context switch R0-R3 and the control registers). How do I know for sure that my ISR will not mess up R4-R11 registers to the interrupted process? Does the compiler do anything to protect these registers?

thanks..

Eric

  • TI__Guru**** 249260 points

    Please read about the __interrrupt keyword in the ARM compiler manual.  Any function marked with __interrupt preserves all the registers it modifies.  

    Thanks and regards,

    -George

  • in reply to George Mock
    TI__Intellectual 795 points

    George

      thanks for you quick response. In our application, depending on the setting, we may need to call some API functions (with parameters) directly from ISR. These functions are organized in a table and there are a few hundreds of them. From my understand these function can not have _interrupt keyword. I am afraid that these functions will use R4-R11 and mess up the interrupted thread.

      Do I need to manually push these registers in the begining of the ISR and pot them out at the end of the ISR?

    thanks...

    Eric

     

     

  • in reply to Eric Zhang16395
    TI__Guru**** 249260 points

    Eric Zhang16395 said:
    Do I need to manually push these registers in the begining of the ISR and pot them out at the end of the ISR?

    No. If an ISR, marked with the __interrupt keyword, calls a function, the compiler generated code preserves all the registers.

    Thanks and regards,

    -George

  • in reply to George Mock
    TI__Intellectual 795 points

    George

       You are right about the R4-R11 registers. I read the ARM procedure call standard one more time (AAPCS). The Callee will preserve them. However, it seems to me that the "_interrupt" keyword isnot be needed for ARM Cortex3/4 family because the Cortex hardware does the R0-R3 and special registers stacking automatically. So the interrupt handlers can be treated as regular sub-routines from compiler point of view. It does not need to context switching those scratch registers.

    Thanks...

    Eric