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Bug in CGT Assmbler: Does not respect --ual for ARMv5TE

42Bastian
Expert 1430 points

Compiling for ARMv5TE with UAL syntax does not Work. This seems to be an old bug (since 4.9.6): .thumb bne.n dd nop dd: This code compiles fine with IAR and GCC and should also with CGT with --ual, but doesn't.

  • TI__Guru* 84285 points

    RVDS 5.01 does not accept it for --cpu=5TE:

    Error: A1617E: Specified width is not supported by the current instruction set.

    If you disassemble the object file generated by IAR and GCC, what is the encoding of the instruction?  For Cortex-A8, for instance, the TI toolset gives:

    000000:               .thumb
000000: D100             BNE             0x00000004
000002: BF00             NOP
000004:              DD:
000004: BF00             NOP
  • in reply to Archaeologist
    Expert 1430 points
    I tried out IAR, GCC and Keil (ARM). All accept UAL correctly. Only CGT does not, though the manual says so.
    Here my results. You see, for Thumb-2 the compilers generate the real NOP, else the Thumb mov r8,r8.
    GCC:
-------
	.syntax unified
	.text
	.thumb
	bne.n dd
	nop
dd:	nop


armv5te
00000000 :
   0:   d100            bne.n   4 
    
   2:   46c0            nop                     ; (mov r8, r8)
   4:   46c0            nop                     ; (mov r8, r8)

armv7a

   0:   d100            bne.n   4 
    
   2:   bf00            nop
   4:   bf00            nop

IAR
--------

	SECTION .text:CODE(2)
	THUMB
	bne.n dd
	nop
dd:
	nop

	END


armv5te
00000000 :
   0:   d100            bne.n   4 
   2:   46c0            nop                     ; (mov r8, r8)
   4:   46c0            nop                     ; (mov r8, r8)

armv7a

00000000 :
   0:   d100            bne.n   4 
   2:   bf00            nop
   4:   bf00            nop

Keil/ARM
--------
	AREA exception_code,CODE
	THUMB
	bne.n dd
	nop
dd
	nop

	END


armv5te:
        0x00000000:    d100        ..      BNE      {pc}+0x4 ; 0x4
        0x00000002:    46c0        .F      MOV      r8,r8
        0x00000004:    46c0        .F      MOV      r8,r8

Cortex-R4

        0x00000000:    d100        ..      BNE      {pc}+0x4 ; 0x4
        0x00000002:    bf00        ..      NOP
        0x00000004:    bf00        ..      NOP
    Cheers
  • in reply to Archaeologist
    Expert 1430 points
    RVDS 5.01 does not accept it for --cpu=5TE:
    Error: A1617E: Specified width is not supported by the current instruction set.
    How does you source look like? Did you use "THUMB" or "CODE16" ?
  • in reply to Archaeologist
    Expert 1430 points
    For the sake of completeness:
    DS-5 (5.16.0) compiles the code with --cpu=5te correct:
    	AREA text,CODE

	THUMB
	bne.n dd
	nop
dd
	nop

	END
    Result:
    ** Section #1 ER_RO **

        0x00008000:    BNE      {pc}+4 ; 0x8004
        0x00008002:    MOV      r8,r8
        0x00008004:    MOV      r8,r8

    So it is only CGT AFAICS which does not support UAL correctly!
    
Cheers,
  • in reply to 42Bastian
    TI__Guru**** 249260 points

    Thank you for submitting a test case.  I can reproduce the problem.  I filed SDSCM00048976 in the SDOWP system to have this addressed.  Feel free to follow it with the SDOWP link below in my signature.

    Thanks and regards,

    -George