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CCSv5 multicore debug question



Hello,

I'm debugging a single-image multicore application on a custom C6678 hardware.
The program gets started with CCS as follows: CCS is only connected to core 0. When loading the program, my .gel script starts the slave cores, which are waiting in the ROM Bootloader (RBL) for the boot magic address. They start an initialization routine which copies all private sections from core 0. Then all cores start the program itself (_c_int00()).

Everything is working fine, but as soon as I establish a connection to a slave core after the program was started, the program counter changes to address 0x20B00000 (RBL) on this core. This only happens if I do a System Reset before loading the program. But I need the System Reset to make sure everything gets initialized properly. It's like CCS remembers the System Reset and executes a core reset after a new connection.

Is there a way to avoid this behavior?

Thanks,
Ralf

  • Hi Ralf,

    What exact version of CCSv5 are you using? Provide the full version number (ex: CCSv5.5.00077).

    Thanks

    ki

  • I'm using Version 5.5.00077.

    Thanks,
    Ralf

  • Ralf Goebel said:
    This only happens if I do a System Reset before loading the program. But I need the System Reset to make sure everything gets initialized properly. It's like CCS remembers the System Reset and executes a core reset after a new connection.

    A System Reset is a system level warm reset that will reset all cores on the device in a multi-core device and peripherals. It has the same effect of pushing the nRESET pin on the board. In principle, the warm reset resets everything except the debug logic.

    So the behavior you see is expected. It's not that the core is getting reset on a new connection. The core was already reset before the connection when you issued the system reset before program load. It reset all the cores then.

    Thanks

    ki

  • Hi Ki,

    I understand that the System Reset will reset all cores. My .gel script executes the System Reset within OnPreFileLoaded() on the master core:

    GEL_AdvancedReset("System Reset");

    After the program is loaded, the .gel script automatically sets the boot magic address for each slave core and then it starts the slave cores.

    I can see that all slave cores are running the program as expected: the slave cores communicate with the master using IPC. But as soon as I establish a connection to a slave, the core gets reset again!

    Thanks,
    Ralf

  • Ah, I get it now. Sorry for not understanding it sooner.

    I'm wondering if you are running into a known issue (SDSCM00049154) where a CPU reset gets triggered on a target connect for the C66x DSP. It was a similar environment (multi-core device, using IPC, etc). This issue was found on CCSv5.5 (worked fine in 5.4). Issue is currently under investigation.

    Thanks

    ki

  • I just tested this with CCSv5.4 and it shows the same behavior.

    But I found out that it depends on the emulator.
    The core gets reset when using one of the following emulators: SD XDS200, SD XDS560v2 LC, SD XDS560v2 STM.
    There is no reset when using the SD XDS510USB plus.

    Thanks,
    Ralf

  • Ralf Goebel said:
    I just tested this with CCSv5.4 and it shows the same behavior.

    Was this a clean 5.4 install (no emulator pack update)?

    Ralf Goebel said:
    There is no reset when using the SD XDS510USB plus.

    This is not surprising. That is because SD has their own drivers for their XDS510USB while the rest of those emulator types (SD or not) leverage TI's drivers.

  • It is a clean installation (5.4.0.00091) with no updates.

    Ralf

  • The same problem occurs with fresh installations of CCSv5.3 and CCSv6 Beta 2.

    Please let me know if you need mor information.

    Ralf

  • Hi ki,

    Do you know if there are any news about this problem?

    Thanks,
    Ralf

  • Hi Ralf,

    CCSv6 beta 4 will be available sometime at the end of this month. When it is available, could you download it and give it a try. There has been a recent fix that I'm hoping will address your issue.

    Thanks

    ki

  • Thanks for this information ki, I will give it a try.

    Ralf

  • Hi ki,

    it seems that beta 4 solved the problem.

    Thanks a lot!
    Ralf