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cycle accurate simulator for C665x

Weichun Yuan
Expert 1210 points

We are running C6657 on CCS 5.3.1 and would like to run a cycle accurate simulator to find out the MIPS needed without inpact from memory and then compare it with cycle approximate simulator  to find out the impact of cache and external memory.

We only find C6657 functional simulator and C667x cycle approximate simulator. Is there a C6657 (or C667x) cycle accurate simulator we can use or can we reconfigure the cycle approximate simulator not to include the cycles due to memory interface?

  • 0
    TI__Guru* 81335 points

    Hi Weichun,

    I have moved your thread to CCS forum to get appropriate response.

    Thanks.

  • 0 in reply to Raja
    TI__Intellectual 1420 points

    Hi Weichun,

    You are right, we dont have C6657 Cycle accurate simulator config.

    Can you kindly go though the user guide for Keystone simulators at http://processors.wiki.ti.com/index.php/TCI6616/C6670/TCI6608/C6678/TCI6618_Device_simulator_User_Guide

    that details the list of configurations and defines what we mean by cycle approximate simulator in terms of validation and scope. Please  get back with any more questions you may have.

    regards,

    Sheshadri

     

  • 0 in reply to Sheshadri Chakravarthy
    Expert 1210 points

    Hi, Sheshadri,

    thanks a lot for the information.

    I would like to run the simulator to get the cycles as if all the data and code are in L1 (without any wait state), so that I can find out what the cycle is without impact of memory. -- Is there a way I can do that with the cycle proximate simulator?

    I would then compare it with the result of enabling cache. Do I understand properly that if I choose DDR speed to be 1333 on cycle approximate simulator, then set L1DCFG, L1PCFG and L2CFG all to be 7, I should be able to run it with L1D/L1P/L2 configured.

    Do I understand this corrrectly?

    thanks

    Weichun

  • 0 in reply to Weichun Yuan
    TI__Intellectual 1420 points

    Weinchun,

    We expose 2 cycle related counters, one is call Cycle.CPU and another cycle.Total. If you look at cycle.CPU count, it will show you CPU cycles only without any memory wait states. The cycle.total would include wait states.

    You have choose "Run->Clock->setup" and in the dropdown select "cycle.CPU". Then do Run->clock->enable. This will show an yellow clock at the bottom of CCS. Run your application and note down this value at the end.

    Repeat the above for cycle.total and again get the value at the end of the run. You can use these values to compare.

    regards,

    Sheshadri

     

     

  • 0 in reply to Sheshadri Chakravarthy
    Expert 1210 points

    Hi, Sheshadri,

    this is to run using clock manually, but I would like to run through a test vector of ~50,000 frames and get the average and worst case MIPS. The profile seems to be easier for this task. Is there a way that I can get these two counts using profiling?

    thanks

    Weichun

  • 0 in reply to Weichun Yuan
    TI__Intellectual 1420 points

    Hi Weinchun,

    If you have to use automation, please refer to below docs on how to setup and get count for clock event through CCS  debug server sccripting interface.

    • CCSv4: '<INSTALL DIR>\ccsv4\scripting\docs\DS_API/com/ti/debug/engine/scripting/ProfileClock.html
    • CCSv5: '<INSTALL DIR>\ccsv5\ccs_base\scripting\docs\DS_API/com/ti/debug/engine/scripting/ProfileClock.html
    • ccsv6/ccs_base/scripting/docs/DS_API/com/ti/debug/engine/scripting/ProfileClock.html

    Typically, you need to setup the clock event for "cycle.Total" or "cycle .CPU" through the APIs described in above doc and collect the event count in 2 separate runs.

    Something like below steps

    1. Evt_id = ..getEventID(“cycle.Total”)
    2. ..setCurrentEvent(evt_id)
    3. RUN the simulations ….
    4. Long Val = ..read()

     regards,

    Sheshadri