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CCS - C6678 Simulator : manually triggered system interrupt not recognized by simulator?

AnBer
Mastermind 30395 points


Team,

I am using the C6678 Device functional sim (little Endian) from CCSv5.5.

I am able to run the basic EDMA CSL example located at the below wiki post (see 2476.main.txt attachement) on it:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/177116.aspx
Following the CIC0 system event 6 (that correspond to EDMA event) the CPU core 0 receives the interrupt event and runs the ISR accordingly.

Now I want to check that I can manually trigger the same interrupt just by writing to the "System Interrupt Status Raw/Set Registers" (see SPRUGW4A page 16 and 22).
When I write 0x40 (that correspond to the event 6) at 0x02600200 via the debugger I can see that the "System Interrupt Status Enabled/Clear Registers" at 0x02600280 is set accordingly with 0x40 meaning that the event was recognized.

However the Core 0 does not seems to recognize the interrupt as it does not jump to the ISR.
I don't think it is the expected behavior. Could you please confirm? My understanding is that writting to "System Interrupt Status Raw/Set Registers" is equivalent to have a system event generated by the on-chip peripherals.

I unfortunately do not have the EVM to test it on a real silicon.

Thanks and best regards,

Anthony

  • TI__Intellectual 1420 points

    Hi Anthony,

    I think memory window writes to the register should trigger the event from DMA. Are you running the simulator after setting up the values? If not please try that and let us know.

    regards.

    Shesha

  • in reply to Sheshadri Chakravarthy
    TI__Mastermind 30395 points

    Hi Shesha,

    Yes I am running the simulator after setting up the value.

    Ater I write 0x40 to 0x02600200 the CPU keeps executing the below loop as the ISR did not run (ie ISR did not change the flag variable):
    while (flag != 1) {
            printf("wait for flag = 1\n");
        }

    Anthony

  • in reply to AnBer
    TI__Intellectual 1420 points

    Hi Anthony,

    Can you check if interrupt for generated from DMA and arrived at CPU boundary, just to be sure. YOu can enable an interrupt trace at DSP CPU boundary by following below steps.

    Open and edit <CCS installaiton>\ccs_base\simulation_keystone1\bin\configurations\tisim_c6678_pv.cfg for example if you are using device functional sim variant.

    Please add below line after END HP2; inside the tisim_c6678_pv.cfg

     CPU_INTERRUPT_TRACE_FILE dsp_interrupt_trace.txt;

    After you run the simulator, you will find interrupt arrived and taken status printed in this file, dsp_interrupt_trace.txt whoch would be generated in <CCS installaiton>\ccs_base\simulation_keystone1\env\ccs\drivers folder. PLease share this file with me to analyse further.

    regards,

    Shesha

  • in reply to Sheshadri Chakravarthy
    TI__Mastermind 30395 points

    Hi Shesha,

    Please find below the dump of dsp_interrupt_trace.txt.

    In case 1:
    EDMA runs and generate an event (CIC0 system event 6) up to the CPU core 0 that receives the interrupt event and runs the ISR accordingly.

    I get:

    (A)rrived|(T)aken:Interrupt no:Core cycles
    ------------------------------------------
    A:4:3286
    T:4:3289:0xc0015b4
    A:4:13626
    T:4:13629:0xc001666

    In case 2:
    I just comment out the CSL_edma3HwChannelControl() fct (at line 208) so that not EDMA transfer take place. Nothing else is changed in the code used in case 1.
    I write 0x40 to 0x02600200 to fake the EDMA event.
    I can see that 0x02600280, 0x02600300 and 0x02600380 are set to 0x40.

    I get:

    (A)rrived|(T)aken:Interrupt no:Core cycles
    ------------------------------------------

    I enclosed the two .out files and the .c file in case you want to try.
    No need to recompile, you can just load the .out and put a BP in the .c file.

    Anthony

    Basic_edma_CSL_int.zip