Hello,
I'm currently working on optimizing a high frequency interrupt on a C6472. I'm attempting to understand why it is taking so long. System analyzer states that it takes on average 4us to complete. When I turn on a hardware count event which counts cpu cycles between the beginning and end of my ISR (inclusive of subroutines) it comes back with 470 cpu cycles. With a 625MHz clock, that is 5x faster than 4us.
Is the count even acting like I expect? based on system performance, the 4us from system analyzer looks correct.
I was hoping to avoid placing lots of Log_write statements in my code, and just use the same binary and move the count event start and stop locations.
Thanks