PLL2 PLLDIV1 register address - datasheet discrepancy? RGMII EMAC setting

David Knowles

Other Parts Discussed in Thread: TMS320C6455

I'm trying to setup my 6482 to use RGMII - and the datasheet says you must set the PLL2 D1 (PLLDIV1 ?) register to 4 (divide by 5) for this to work. The datasheet says that PLLDIV1 for PLL2 is located at memory address 029C 0118, but in Code Composer (V6) this register appears to be located at memory address 029C 0114, and called PREDIV, instead of PLLDIV1. (There is no PLLDIV1, and no PLL2 register at address 029C 0118). I did not see any corrections to the datasheet in the 6482 errata. Can anyone confirm this? Is Code Composer wrong, or is the datasheet wrong? They seem to contradict.

over 11 years ago

0 Sivaraj Kuppuraj over 11 years ago

TI__Mastermind 35645 points

Hi,

Team will respond to your request as soon as possible.

Thanks & regards,

Sivaraj K

0 Senthilkumar Srinivasan over 11 years ago

TI__Mastermind 43660 points

Hello David,

TCI6x devices are supported directly through Local Field Applications Engineers (FAEs.) These devices are not supported on the E2E forum. Please contact your local FAE for support of these devices. If you are not sure who your local FAE is, then please contact your local technical sales representative and they will be able to put you in contact with your local FAE.

Regards,

Senthil

0 David Knowles over 11 years ago in reply to Senthilkumar Srinivasan

Prodigy 120 points

I believe the 6482 and 6455 are configured the same as far as the CORE and the EMAC goes with respect to the PLL. How about an answer for the 6455? Perhaps all C64x are the same? I have sent an e-mail to my FAE.

0 Titusrathinaraj Stalin over 11 years ago

TI__Guru** 116100 points

Hi David,

Have you selected the "C6455" in CCSv6 and checked whether the same behavior exists in that too ?

Could you give screen shot of the project properties to check the target and type.

How did you selected the target while you creating the new project ?

C64xx or exact name like TCI6482 ?

Have you changed the code for D1 divider and able to get expected freq for EMAC & probed through DSO/CRO ?

Actually currently I don't have the C6455 and TCI6482 board with me to check.

I hope, data sheet gives correct MMR value rather than CCS.

0 David Knowles over 11 years ago in reply to Titusrathinaraj Stalin

Prodigy 120 points

The project properties is a rather large dialog with lots of tabs and folders to open in CCS 6 (We have both CCS 5.5 and 6 in use here).

Under General, Main tab, I have the C6000 Family, and Variant TMS320TCI6482. I tried switching to Variant TMS320C6455, and got the same results. It is not clear to me if this changes something with the compiler, or the debugger, as CCS is both. I am launching the Target configuration called TMS320TCI6482.ccxml which I believe came with Code Composer Studio V5.5. We selected a project template dsk6455 Examples, and picked the hello example to create the new project. We are currently struggling to get the EMAC working (thus the question). So far it seems to work best (we get correct clock out, and are able to TX data, but not RX), if we don't configure the PLL2 at all. It defaults to divide by 2, but the datasheet indicates we need to divide by 5 for RGMII. Since I'm not configuring the PLL2 at all, it is not clear to me, which address I should use to configure it. All my attempts to configure it resulted in non working EMAC of some variety.

0 David Knowles over 11 years ago in reply to David Knowles

Prodigy 120 points

0 David Knowles over 11 years ago in reply to David Knowles

Prodigy 120 points

The screen shot shows the 6482 registers for PLL2, and the Memory Browser for the memory associated with those registers. I was connected to the DSK in this instance, and the DSP software initialized the PLL2 for divide by 5 according to the datasheet. I used Code Composer to update the "PREDIV" register (aka PLLDIV1?) with an invalid value (0x800D) to show that memory address 0x029C0114 was updated, and not 0x029C0118, which still has the correct value (0x8004 = enabled, divide by 5). I will continue to troubleshoot the problem assuming the datasheet is correct, and Code Composer is wrong about the name/address of this register. So far I'm still having better luck with my RGMII if I use the divide by 2 setting (default - no update to PLL2) than if I try and update PLLDIV1 with the value for divide by 5 which the datasheet says is required. ("A. /x must be programmed to /2 for GMII (default) and to /5 for RGMII.") By default memory address 0x029C0114 (PREDIV reg) comes up all zeros at power up.

PLL1 seems to work as described in the datasheet.

0 Titusrathinaraj Stalin over 11 years ago in reply to David Knowles

TI__Guru** 116100 points

Hi David,

I think, CCS forum guys can answer much better on this.

Moving your query to CCS forum.

0 desouza over 11 years ago in reply to David Knowles

TI__Guru**** 171819 points

Hi,

Looking at the device XML files (the files that describe several inner details of the device) for both the TCI6482 and C6455, I can see they use the same Module XML file (the file that describes the peripheral registers) for both PLL1 and PLL2. Therefore the registers displayed will be the same for both register sets.

These files were sent to us in the CCS group years ago by the device group, and unfortunately bugs like these went unnoticed all this time. Given a fix to this may or may not be necessarily trivial, as I see many differences between the two register sets. Most seem simply removed from PLLC2, but I will try to get someone from the device group to give a more educated comment on that and I can release a patch. I am unsure how long this will take.

In the meantime, if you are interested in taking a look at the files, do the following.

- go to directory <CCS_INSTALL_DIR>/ccsv6/ccs_base/common/targetdb/devices
- open the file <c6455.xml> or <tci6482.xml> on a text editor. Lines 34/35 (64/65 for the second file) have the instantiation of the PLLC1/PLLC2 peripherals. On the PLLC2 instance, change the "href=" and "xml=" references to point to a different filename, such as <cslr_pllc2.xml>.
- go to directory <CCS_INSTALL_DIR>/ccsv6/ccs_base/common/targetdb/Modules
- create a copy of the file <cslr_pllc.xml> instantiated above, rename it to whatever was named in step 2 above and open it on a text editor.
- insert and remove the desired registers from this file. Specifically for the PLLDIV1 register, I noticed the file <cslr_pllc_001.xml> in the "Modules" directory above contains it, which could be perhaps used as a good template to add it.
- a CCS restart is required to properly pick up all the changes

I apologize for the inconvenience,

Rafael

0 David Knowles over 11 years ago in reply to desouza

Prodigy 120 points

So I think the answer to my question is that the datasheet is correct, and CCS is wrong. I am in no hurry to get a fix for CCS - I can access the register via the memory map if necessary. I just wanted to make sure the DSP code was correct.

So the secondary question becomes, should we set the PLL2 PLLDIV1 register to divide by 2 or divide by 5 for RGMII. Divide by 2 seems to work on the EVM, and Divide by 5 (as the data sheet says is required) does not seem to work. I may have answered my own question.