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LDRD instruction gives missing operands error in CORTEX M4 CCS!!

sreenivasa upadhyaya
Intellectual 805 points
Other Parts Discussed in Thread: TM4C129XNCZAD

Hi all,

I am using CCS studio with TI arm compiler/assembler v 5.5 to build my .asm assembly file for cortex m4 processor.

Instructions like

" LDRD     R4,[R1] ", "STRD     R8,[R5]"  gives " Missing operand(s) "  error.

I have build the same file without any errors using the GNU compiler in CCS.

I referred to many documents online and found LDRD, STRD is supported by cortex m4 and in specific by tiva tm4c129XNCZAD.

Please help me  why this  error is coming.

Thank you.

Regards,

Sreenivasa U

  • 0
    TI__Guru* 84285 points

    Write it in canonical UAL form:

    LDRD R4, R5, [R1]
STRD R8, R9, [R5]
  • 0 in reply to Archaeologist
    Intellectual 805 points

    Hi Guru,

    Thanks a lot for the quick reply.

    I put a random instruction  LDRD     R8,[R1],LR as u suggested and the assembler did not give an error.

    if the existing code is LDRD R4, R5, [R1] what could be its canonical UAL form.?

    After all i dont have any idea about canonical UAL form and the normal form. Can u share documents or links specifying the same.

    Regards,

    Sreenivasa U

  • 0 in reply to sreenivasa upadhyaya
    TI__Guru* 84285 points

    ARM has standardized the syntax of the ARM instructions as UAL (unified assembler language).  This is so that users can write instructions in this syntax and be assured that any vendor's assembler will accept the instructions. One vendor's assembler may accept alternate forms, but every vendor is required to accept the canonical forms described in the architecture reference manual.

    For a quick summary, you should look over ARM's instruction set quick reference cards

    The following instruction is not legal on M4; I don't know where it came from, but I did not suggest it:

    LDRD R8, [R1], LR

    However, it is legal on A8, where its canonical form is:

    LDRD R8, R9, [R1], LR

    The following instruction is already in canonical form:

    LDRD R4, R5, [R1]

    LDRD reads a double word, so it needs two destination registers.

  • 0 in reply to Archaeologist
    Intellectual 805 points

    Hi ,

    Thanks, Lot of things are clarified by ur reply.

    Yes you are right . I am trying to port things from ARM9E to Cortex M4.

     

    Will get back in case of any problems.

     

     

    Regards,

    Sreenivasa U