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AM3359 - Initialization without GEL file

Jakub Lesinsky
Prodigy 50 points

Other Parts Discussed in Thread: AM3359

We are trying to make booting from an SPI Flash memory functional without the GEL file on DRA604. The project we are experimenting with was created as an empty C project in the CCSv5.5 with AM3359 selected as the target platform. The SPI did not work out-of-the-box so we are loading the executable into SRAM using a J-Link Base JTAG probe.

The problem seems to be that the default state of the Thumb bit in CPSR register is set to 1, while the first instruction of the resulting application is a 32-bit instruction (read of CPSR, see the attached disassembly screenshot). The code works properly when we manually change the Thumb bit to 0.

The compiler parameters set by the project are the following:
-mv7A8 --code_state=16 --abi=eabi -me --include_path="C:/ti/ccsv5/tools/compiler/arm_5.1.1/include" -g --define=am3359 --diag_warning=225 --display_error_number --diag_wrap=off


We tried both --code_state=16 and --code_state=32 with no luck.

Is there any way to change the default state of the Thumb bit, or is there an option to compile in a way that the CPSR read instruction would work under the Thumb mode ?

  • 0
    TI__Guru**** 393215 points

    Moving this to the CCS forum.

  • 0
    Prodigy 50 points

    We've sent this to Marc Jüttner, who asked us following questions :

    Please give me some more detailed information :

    - What kind of project do you create (CCS Project, C project, etc.)? Reconstruction steps would be perfect.
    We have used empty C project

    - What compiler do you use (version etc.)?
    TI v5.1.1

    - What target configuration do you choose (e.g. device family, target processor)?
    AM3359

    - What GEL file do you use?
    We are trying to accomplish booting without GEL file

    - What JTAG probe do you use?
    J-Link Base

    - Do you use the Beaglebone? If not, can you reproduce on Beaglebone?
    We can test it on a Beaglebone, not tested it yet

    - Which CCS version do you use?
    CCS v5.5

    - What version of the CCS emulator pack do you use?
    ti_j-link_support_setup_0.1.0.5

  • 0
    TI__Guru**** 171729 points

    Hi,

    This question is very intrinsic to the CortexA core itself and not necessarily related to CCS, but I can make a few comments:

    - According to the Cortex A8 TRM, the T bit is set depending on the input passed to the core via the CFGTE signal.

    - Still according to the Cortex A8 TRM, the CFGTE is sampled during reset and is a signal (an internal "pin" to the core). This "pin" may or may not be tied to an external pin of the device itself. 

    - Looking at chapter 26, table 26-7 of the AM335x TRM, the only pins that seem to control the boot process are SYSBOOT pins, but I can't spot anything that controls the boot state mode of the device.

    - My previous knowledge from other projects is that the CortexA8 on the AM335x devices always boots in ARM mode - I can only assume the CFGTE signal is internally tied to "0" (check the screenshot below, with my BBone White immediately fresh from reset).

    Therefore, I find interesting your observation that the processor has the T bit set after reset - I wouldn't expect it so, but perhaps there is something else going on with the processor, or perhaps the type of reset applied is a "warm" reset that does not fully mimic its status as if it was coming from a power up. That also explains why resetting the T bit makes the code work - the first instructions of your screenshot are ARM.

    One last detail that may help you with the bootstrap sequence is to look at how the TI compiler performs it. 

    - Go to the directory C:\CCSv6_0_1\ccsv6\tools\compiler\arm_5.1.1\lib
    - Unzip the file <rtssrc.zip> to a subdirectory (I usually use src)
    - Go to the directory where you extracted the .zip and open the file <boot.asm> in a text editor.

    Unfortunately I am not the best person to talk about the internal aspects of the device itself, therefore I would ask you to also check with the experts at the Sitara forum.

    Hope this helps,

    Rafael

  • 0 in reply to desouza
    Prodigy 50 points
    Hi,

    Thank you very much for your help, CFGTE signal seems to be the problem, however we are not able to find any documentation concerning its state in AM3359

    Both DRA604 and AM335X EVM have Thumb bit 1 after issuing reset.

    Thanks aswell for boot.asm location, we have found temporary workaround, since first arm instructions are only used to read CPSR and change the state of T-bit, we've commented them out, and app works straight away, only problem though is that rest of our binaries are build with 32 bit mode instructions.

    We have placed this question in Sitara forums, but it has been moved here. Do you have any collegues, that specialize in this area ? We would be greatfull if you could point them here.
  • 0 in reply to desouza
    Prodigy 50 points

    Hi,


    Today we have discovered interesting things

    with J-link Base:

    Thumb bit is initially 1, and stays 1 after reset

    with XDS200:

    Thumb bit is initially 0, and stays 0 after reset

    with XDS560:

    Thumb bit is initially 1, and gets changed to 0 after reset

    Hope this helps someone, however this does not specificly tell us, what is the default state of the Thumb bit.