Are the parallel processing related to software pipeline?

SuitJune Young

according to the docs about the dsp optimization,The C6000 DSP core can do the parallel processing with the smaller function unit,such as M1,M2,S1,S2. And DSP core can also do the software pipeline.

Are the two features related?

I think the DSP core can pipeline code with the parallel processing unit(M1,M2,S1,S2....), or else,it can NOT be pipelined.Is it right?

BR!

over 10 years ago

0 George Mock over 10 years ago

TI__Guru**** 249260 points

The C6000 CPU has features which are specifically designed to be used in loops scheduled with a technique called software pipelining. These CPU features include 8-way parallelism and dedicated instructions like SPLOOP. The method by which most users take advantage of these features is to write C code. The C6000 compiler generates high throughput loops from the C code. These loops are scheduled with software pipelining.

Thanks and regards,

-George

0 SuitJune Young over 10 years ago in reply to George Mock

Genius 3985 points

If the each loop is dependent.I mean that the result of loop N is used as the input of loop N+1, in this case, could we use Software pipeline?If not,how could we optimize and speed the algorithm code?

BR!

0 George Mock over 10 years ago in reply to SuitJune Young

TI__Guru**** 249260 points

You voice a valid concern. If the result of loop iteration N is an input to loop iteration N+1, then the opportunity for acceleration through software pipelining is reduced. The compiler automatically recognizes this situation and handles it appropriately. Such loops are said to contain loop-carried dependencies. Please see this wiki article for more discussion and how you can address them.

Thanks and regards,

-George

0 SuitJune Young over 10 years ago in reply to George Mock

Genius 3985 points

Thanks for your reply.

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Are the parallel processing related to software pipeline?