Hello all,
We are using TDA2xx SoC and XDS560v2 Pro Trace emulator. When I tried to do the Stall profiling forC66xx _DSP1, it gives error "Could not run analyzer on c66xx_DSP1. Cause: This device is not supported by the receiver". Is it so?
Even I am not able to do any functionality comes under Tools>Hardware Trace Analyzer in CCS.Also tried with XDS560v2 STM.
Please let me know the way to analyze the stall profiling on TDA
Thanks.
Hi Desouza
Please see the log below from launching Target Configuration file to loading binaries to all cores
Cortex_M4_IPU1_C0: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> DRA7xx C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> DRA7xx C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> DRA7xx Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> DRA7xx Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> DRA7xx Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> DRA7xx PG1.0 GP device <<<---
CortexA15_0: GEL Output: --->>> The core is in non-SECURE state. <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking...
CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: PER DPLL already locked, now unlocking
CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking....
CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: EVE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: EVE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output: DEBUG: Overall DDR configuration
CortexA15_0: GEL Output: DEBUG: EMIF1 and EMIF1 DDR IOs config (CTRL_MODULE_CORE_PAD module)
CortexA15_0: GEL Output: DEBUG: DDR PHY config (CTRL_MODULE_WKUP module)
CortexA15_0: GEL Output: DEBUG: EMIF1 ctrl + associated DDR PHYs initial config (EMIF1 module)
CortexA15_0: GEL Output: DEBUG: EMIF2 ctrl + associated DDR PHYs initial config (EMIF2 module)
CortexA15_0: GEL Output: DEBUG: Setting LISA maps in non-interleaved dual-EMIF mode
CortexA15_0: GEL Output: >> Default memory map selected-
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DRA7xx Begin All Pad Configuration for Vision Platform <<<---
CortexA15_0: GEL Output: --->>> DRA7xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<---
CortexA15_0: GEL Output: --->>> DRA7xx Begin GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> DRA7xx End GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> DRA7xx Begin GMAC_SW RGMII0 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> DRA7xx End GMAC_SW RGMII0 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> DRA7xx Begin GMAC_SW RGMII1 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> DRA7xx End GMAC_SW RGMII1 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> DRA7xx End All Pad Configuration for RGMII usage on EVM Platform <<<---
CortexA15_0: GEL Output: --->>> DRA7xx End All Pad Configuration for Vision Platform <<<---
CortexA15_0: GEL Output: --->>> DRA7xx Target Connect Sequence DONE !!!!! <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: Output: Configuring EVE1 MMU TLB entry 1
CortexA15_0: Output: Configuring EVE1 MMU TLB entry 2
CortexA15_0: Output: MMU configured for EVE1
CortexA15_0: GEL Output: --->>> EVE1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: Output: Configuring EVE2 MMU TLB entry 1
CortexA15_0: Output: Configuring EVE2 MMU TLB entry 2
CortexA15_0: Output: MMU configured for EVE2
CortexA15_0: GEL Output: --->>> EVE2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE3SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: Output: Configuring EVE3 MMU TLB entry 1
CortexA15_0: Output: Configuring EVE3 MMU TLB entry 2
CortexA15_0: Output: MMU configured for EVE3
CortexA15_0: GEL Output: --->>> EVE3SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE4SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: Output: Configuring EVE4 MMU TLB entry 1
CortexA15_0: Output: Configuring EVE4 MMU TLB entry 2
CortexA15_0: Output: MMU configured for EVE4
CortexA15_0: GEL Output: --->>> EVE4SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
Using Spectrum 560v2 STM >>>>>>
Also getting same with Spectrum XDS560v2 Pro Trace emulator.
Please correct me : Does Emulator needs device file? which is stored at installed directory "C:\ti\ccsv5\ccs_base\emulation\analysis\xmldb\trace_config\devices"
If yes, then where should I get this file?
Thanks.
