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Error in debug mode

John Pillai
Intellectual 550 points

Other Parts Discussed in Thread: DM3730

C64XP_0: Error connecting to the target: (Error -1178 @ 0x6D) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.450.0)

I see the following above error when I launch debug session  .I am using CCS 6 with XDS560V2 STM any leads on how to solve this issue will be of greater help.

  • 0
    TI__Guru**** 171649 points
    Hi,

    I apologize for the delay. Are you still having this issue?

    I would double-check all connections and the tab Advanced of the Target configuration file, more specifically the settings for the JTAG clock (may be too high) or if it may be set to adaptive (C64x devices require fixed clock).

    Obviously that all this assumes the device is fully powered as well as its clock/PLL circuitry.

    Hope this helps,
    Rafael
  • 0 in reply to desouza
    Intellectual 550 points

    Hi desouza,

    thank you for your reply. I a using a BeagleBoardXM and spectrum digital XDS560 . I have found that  before connecting to C64 i need to connect to ARM that does some initialization on clocks etc using GEL files and after those reset if I run IVA2 core reset gel file  and then connect to C64 I am successfully  connected and then i can load my program.

    hence, my understanding The ARM has to be up with some basic initialization and then the DSP can be connected.Correct me if I am wrong

    I have few more question : 1. any documents on how this GEL files works along with XDS? without the gel file, the configuration can be loaded in boot code ?

  • 0 in reply to John Pillai
    TI__Guru**** 171649 points
    Hi,

    Thanks for providing the device details; your understanding is correct: on the DM3730 device, the DSP is a slave core to the ARM, hence it must be powered up and released from reset by the latter. The GEL file has the necessary code to perform this.

    A reference is shown at the link below:
    processors.wiki.ti.com/.../GSG:Connecting_to_slave_cores_in_SoC_devices_v5

    The GEL file is a text file that simply issues a sequence of commands to the CCS debugger and, being syntatically identical to the C language, can be easily included in the boot code of your application save the built-in GEL functions.

    Details about how the GEL is included into the debugging process is shown at the page below:
    processors.wiki.ti.com/.../Debug_Handbook_for_CCS

    There is also an ancient document about GEL but has good fundamental information:
    www.ti.com/.../spraa74a.pdf

    Hope this helps,
    Rafael