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Creating rtsv6M0_T_le_eabi.lib in CCS

Devaraj Premanathan
Prodigy 130 points

I am using 6.1.0.00104 and I do not find the rtsv6M0_T_le_eabi.lib in

ccsv6\tools\compiler\ti-cgt-arm_5.2.2\lib area. I would like to build this library. What is the procedure to do it?

Additionally, I am working on a design that supports a hardware divider. I would like to generate a library where the 32-bit division uses the hardware divider. What is the procedure to to this?

  • 0
    Guru 92251 points

    Devaraj Premanathan said:
    I am using 6.1.0.00104 and I do not find the rtsv6M0_T_le_eabi.lib in

    ccsv6\tools\compiler\ti-cgt-arm_5.2.2\lib area. I would like to build this library. What is the procedure to do it?

    The Linker should automatically build the rtsv6M0_T_le_eabi.lib library the first time the library is used in a build, by using mklib.

    When the Linker needs to automatically build the library, the follow output was the result of a successful build:

    <Linking>
    warning #10366-D: automatic library build: using library "/opt/ti/ti_ccs6_1/ccsv6/tools/compiler/ti-cgt-arm_5.2.4/lib/rtsv6M0_T_le_eabi.lib" for the first time, so it must be built. This may take a few minutes.
    Finished building target: Cortex_divide.out

    See the Library-Build Process section in the ARM Optimizing C/C++ Compiler v5.2 User's Guide SPNU151J for details.

    Devaraj Premanathan said:
    Additionally, I am working on a design that supports a hardware divider. I would like to generate a library where the 32-bit division uses the hardware divider. What is the procedure to to this?

    Reading the compiler documentation I can't see an option to specify if to use the hardware divider. Can you clarify which device you are using, since the library name is for a Cortex-M0 which I don't think supports hardware divide.

    Edit: Updated to show output from successful automatic build of library.

  • 0 in reply to Chester Gillon
    Guru 92251 points

    Chester Gillon said:
    Reading the compiler documentation I can't see an option to specify if to use the hardware divider.

    From a test program, using the TI ARM compiler v4.4.4 --silicon_version,-mv (Target Processor version) compiler switch selects if the compiler generates the hardware divide instructions:

    1) Using -mv7M4 (Cortex-M4) the compiler emits the UDIV (unsigned) and SDIV (signed) hardware divide instructions.

    2) Using -mv7M3 (Cortex-M3) the compiler emits the UDIV (unsigned) and SDIV (signed) hardware divide instructions.

    3) Using -mv6M0 (Cortex-M0) the compiler calls the __aeabi_uidivmod (unsigned) and __aeabi_idivmod (signed) software divide routines.

    This agrees with the table in http://en.wikipedia.org/wiki/ARM_Cortex-M#Instruction_sets which says that the Cortex-M3 and Cortex-M4 support hardware divide, but the Cortex-M0 doesn't.

  • 0 in reply to Chester Gillon
    Prodigy 130 points

    Based on the response provided, I was able to use the instructions in  ARM Optimizing C/C++ Compiler v5.2 User's Guide SPNU151J  to build the library. The linker hower did not build the library automatically. mklib had to invoked to build the library.