Failure in connection between XDS560v2 STM and target

Hello,
What is your target?

Thanks
ki

Hello Ki,

Target: Custom board with J6Eco.

QNX is used on the A15 and Sysbios on the M4.We are currently checking whether the M4 code has started running.

I am using Spectrum Digital XDS560v2 along with CCS for debugging.When I start the target, I executed dbgjtag to check the connection of JTAG with target and everytime I get this error.

 

I checked the JTAG debugging blogs and nothing helped

Thanks,

Vijaya

 

Hello Ki,

I have one doubt.There is 20-pin connector on the JTAG Emulator and on the target 14-pins are present.Attached are the screenshots.I have a custmoized board which will in turn make the 20-pin connector connected to the target.I am not sure where the 3V3SW should be connected.

I will try your suggestion of setting the clock and provide you feedback.

Thanks,

Vijaya

Vijaya,

Our main reference for JTAG hardware implementation is shown at the page below.
processors.wiki.ti.com/.../XDS_Target_Connection_Guide

The schematics diagram you sent is only missing a 100Ω current limiting resistor (to prevent any damage to the JTAG debugger). Check section 7.1 of the page above.

Hope this helps,
Rafael

Hello,

Thanks for your fast  response.

After changing freq to 10.38MHz, I am not getting the JTAG clock error.But instead, I am getting below error:

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\kz0wz6\AppData\Local\.TI\693494126\
    0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'sd560v2u.out'.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'May  6 2013'.
The library build time was '22:11:54'.
The library package version is '5.1.114.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.

An error occurred while hard opening the controller.

-----[An error has occurred and this utility has aborted]--------------------

This error is generated by TI's USCIF driver or utilities.

The value is '-183' (0xffffff49).
The title is 'SC_ERR_CTL_CBL_BREAK_FAR'.

The explanation is:
The controller has detected a cable break far-from itself.
The user must connect the cable/pod to the target.

[End]

Any suggestions?

Thanks,

Vijaya

Vijaya - I just want to confirm that you also configured for "Fixed with user specified faster value" in addition to changing the freq. Assuming you did, Rafael describes the error in the thread below:
e2e.ti.com/.../1080750

Hope this helps
ki

Hello Ki,

Thanks for your response.

I am getting below error now:

%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\kz0wz6\AppData\Local\.TI\693494126\
    0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'sd560v2u.out'.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'May  6 2013'.
The library build time was '22:11:54'.
The library package version is '5.1.114.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '5' (0x00000005).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc

An error occurred while hard opening the controller.

-----[An error has occurred and this utility has aborted]--------------------

This error is generated by TI's USCIF driver or utilities.

The value is '-233' (0xffffff17).
The title is 'SC_ERR_PATH_BROKEN'.

The explanation is:
The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.
An attempt to scan the JTAG scan-path has failed.
The target's JTAG scan-path appears to be broken
with a stuck-at-ones or stuck-at-zero fault.

any suggestions?

Regards,

Vijaya

Have you ever been able to connect to this custom board in the past? Can you attach your target configuration .ccxml file?

Thanks
ki

Hello Ki,

This is the first time I am connecting the emaulator to this board.I have attached the target configuration file.

Thanks,

VijayaDRA7xx_XDS560.zip

Vijaya,

Your .ccxml file looks fine, which makes us second guess your board. Can you check if the board design follows the guidelines shown at the page below?

processors.wiki.ti.com/.../XDS_Target_Connection_Guide

More specifically section 7, which talks about the different circuit configurations.

Hope this helps,
Rafael