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Wrong PLLM Multiplier value for DDR2

Other Parts Discussed in Thread: TMS320DM647, CCSTUDIO

There seems to be a difference for PLL2 multiplier between documentation and actual register reading. In subsystem guide and dm647 data sheet, PLLM value is 0x13 which corresponds to x20. When I read this register on EVM648 board using CCS thru JTAG, I get  0x00000010(x17). Also, the PLLCTL register is 0x00000060 which means PLL2 is in bypass mode. BTW, when I read PLL1 registers, it is what I expected per documentation.

Questions:

1. Has PLL2 multiplier been changed to x17? If so, I need to change CLKIN2 freq on my board.

2. DDR2 memory seems to be fine on EVM648 board. Why is PLLCTL saids PLL2 is in bypass mode?

  • Hi Dan,

    What boot mode is the EVM set to?  Please take a look at the "Using the TMS320DM647/DM648 Bootloader" appnote to understand how the bootloader programs the PLL for each boot mode.  Also, are you loading a GEL file in CCS?  If so, there is a function in the GEL file which runs automatically upon connecting to the device.  This function is likely programming the PLLs and setting up other system configs.

    Regards,

    Brad

  • Hi,

    In addition to what Brad said, Multiplier Value = PLLM + 1.

  • Brad,

     

    The bootloader, subsystem, megamodule, PCI, DDR2 documentations are my favorite night time readings for the past several weeks. The bootloader document talks about cpu pll and not ddr2 pll(pll2). My board's boot mode is PCI slave with no auto-init and in fast boot mode.

      ********* DSP2 Board(dm647) Boot Mode Info ***********
      > [BOOTMODE]  : Slave Mode - PCI Boot No Auto Init
      > [AECLKINSEL]: EMIF3B Clocked From Outside AECLKIN
      > [PCI66]     : No (33 MHz)
      > [HPIWIDTH]  : 16 Bits
      > [FASTBOOT]  : Yes
      > [EMIFBWIDTH]: 8 bits
      > [PCI]       : ON
      > [ENDIAN]    : Little Endian

    On page 48 of subsytem guide, it says "For PLLC1, PLLM defaults to 13h (PLL1 multiply by 20); for PLLC2, PLLM defaults to 13h (PLL2 multiply by 20), PLLM field of PLLC2 is read-only." Below are PLLC2 register values. As you can see, PLLM is 10h, not 13h per subsystem guide. There is no easy way for me to use a scope to measure the actual DDR2 clk freq. I tried to use gel file function to change PLLM to 13h. It didn't change which confirms the read-only statement.

    PLLCTL    00000041
    PLLM        00000010
    PLLDIV1    00A20000
    PLLDIV2    00008031
    BPDIV        00000000
    PLLCMD    00000001
    PLLSTAT    00000004
    ALNCTL    00000000
    DCHANGE    00000000
    CKSTAT    00000000
    SYSTAT    00000001

    So, the question remains- what is the real PLL multiplier value?

    Thanks

  • Yes, I understand that but we are talking about 10h vs 13h.

  • Dan,

    I just tried this on a DM648 EVM, and PLLM for PLL2 came up with the default value of 0x00000013.  Please try  the following experiment:

    - Change the boot mode to Emulation Boot by setting BOOTMODE[3:0] to 0000 using the board switches.

    - Remove the GEL file from your project by Right clicking on it and selecting Remove

    - Remove and reapply power to the board

    - Connect to the board in CCS (Alt-C)

    - Bring up a memory window by clicking View->Memory

    - Enter the address 0x02120110 into the memory window and see if it reads 0x00000013 or 0x00000010

    Thanks,

    Brad

  • Brad,

     

    I just read the memory location of PLLM per your suggestion and I have 13h! All other register values match. It seems unlikely there is a bug just for this register location. What is going on?

  • Dan,

    Something in your system is reprogramming the value from 0x13 to 0x10.  Even though the documentation says this register is Read Only, I am able to change the value by writing directly into the memory window (not sure if the actual multiplier is changing though...).

    Try adding back in your GEL file, while leaving the boot mode in Emulation Boot.  If the value is still 0x13, then it's not the GEL file changing it to 0x10.  In that case, it may be something related to booting.  Is there a PCI host that is booting DM648 through the PCI port that could be reconfiguring the PLL?

    Regards,

    Brad

  • Brad,

    My board is in emulation mode and no gel file. It started up with mem location 0x02120110 at 13h but Register Window in lower right still shows PLLM to be 10h. The PLLM value is always 10h no matter what value I set in 0x02120110. Can you look at your PLL2's register thru the Register Window?

    Thanks

  • Dan,

    It looks like the register view XML source file has a bug.  The register view is populated from the XML file located at:

    C:\CCStudio_v3.3\drivers\TargetDB\Devices\DM648x7.xml

    You can see in this XLM file that the PLL2 register addresses are taken from this file:

    C:\CCStudio_v3.3\drivers\TargetDB\Modules\dm64lc_cslr_pll2_001.xml

    dm64lc is a different device from DM648, and dm64lc's PLLM address offset is 0x104 instead of 0x110 for DM648.  Therefore the value of 0x10 you are seeing for PLLM in the register window is actually the value of address 0x02120104.  You can change the value at this address and see the PLLM value updated.

    I'm going to move this thread to a different forum that has the right people to fix this bug in the XML.  For now, I recommend avoiding the register  view for the PLL registers, and using the memory window instead.

    Thanks,

    Brad

  • Dan,

    I fixed the PLL XML files and attached them to this message.  Drop these files into the C:\(CCS Install Directory)\drivers\TargetDB\Modules directory.

    Also, I have attached an updated DM648x7.xml file that now points to the new PLL XML files.  Please put this file in the C:\(CCS Install Directory)\drivers\TargetDB\Devices directory.

    Hopefully this allows you to View->Registers to see the correct PLL registers.

    Regards,

    Brad

    (Update: Added files as a single .zip file, since multiple attachments weren't allowed)

    dm648_pll_xml_update.zip
  • Brad,

    Sorry, I was away last week. I tried your changes and rebooted my computer but PLLM is still wrong. I saw a file, DM648x7.xml.cache, in C:\CCStudio_v3.3\drivers\TargetBD\Devices. I changed the PLLM offset to 0x110 and it works! I also changes the base addr for cache to 0x01840000 since it is wrong.

    Thanks for all your help.