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Is this a normal output ? What flags do I need ?



I compiled a project with CCS. The code is this:

int main(void) {
    WDTCTL = WDTPW | WDTHOLD;	// Stop watchdog timer

    P1DIR |= BIT0;

    P2DIR &= ~BIT1;
    P2OUT |= BIT1;
    P2REN |= BIT1;

    while (1){

    	if ((P2IN & BIT1) == 0){
    		red_on();
    	}else{
    		red_off();
    	}

    }

	return 0;
}

void red_on(){
	P1OUT |= BIT0;
}

void red_off(){
	P1OUT &= 0xFE;
}

The output is 70 MB. It contains 401 sections. This output was made by a program I wrote because the linux terminal tools don't show them all, just 255.

-File opened
--------------- ELF HEADER ---------------
--Magic number read:                     [ELF]
--Class:                                 [1] (32 bits)
--Endianness:                            [1] (little endian) 
--ELF Version:                           [1]
--OS/ABI:                                [0]
--ABI Version:                           [0]
--7 byte gap read:                       []
--Type:                                  [1] (relocatable)
--Machine:                               [69 (hex)][105 (dec)]
--Version:                               [1]
--Entry Point Address:                   [0x0]
--Program Header Table:                  [0xdbbc]
--Section Header Table:                  [0xdbbc]
--Flags:                                 [0]
--ELF Header size (bytes):               [52]
--Program Header Entry size (bytes):     [32]
--Entries in Program Header:             [0]
--Section Header Size:                   [40]
--Entries in Section Header Table:       [402]
--Index of the string section header:    [401]
--------------- ELF HEADER ---------------
--------------- ELF PROGRAM HEADER ---------------
--------------- ELF PROGRAM HEADER ---------------
--------------- ELF SECTION HEADER (402) ---------------
 Idx  Name             Size      VMA       LMA       File off  Algn  EntSize   Info Type Flags
  0.                   0         0         0         0         0     0         0    0         0       
  1.  __TI_DW.debug_   24        0         0         34        0     4         1352 17        0       
  2.  __TI_DW.debug_   24        0         0         4c        0     4         1398 17        0       
  3.  __TI_DW.debug_   24        0         0         64        0     4         1400 17        0       
  4.  __TI_DW.debug_   24        0         0         7c        0     4         1401 17        0       
  5.  .bss             0         0         0         94        1     0         0    8         3       
  6.  .data            16        2400      2400      94        2     0         0    1         3       
  7.  .TI.noinit       0         0         0         0         1     0         0    8         268435456
  8.  .sysmem          0         0         0         0         1     0         0    8         0       
  9.  .stack           4         43fc      43fc      a4        2     0         0    8         3       
 10.  .text:_isr       32        4400      4400      a4        2     0         0    1         6       
 11.  .cinit           0         0         0         0         1     0         0    8         0       
 12.  .const           0         0         0         0         1     0         0    8         0       
 13.  .cio             0         0         0         0         1     0         0    8         0       
 14.  .pinit           0         0         0         0         1     0         0    8         0       
 15.  .init_array      0         0         0         c4        1     0         0    8         3       
 16.  .mspabi.extab    0         0         0         c4        1     0         0    8         2       
 17.  .infoA           0         0         0         0         1     0         0    8         0       
 18.  .infoB           0         0         0         0         1     0         0    8         0       
 19.  .infoC           0         0         0         0         1     0         0    8         0       
 20.  .infoD           0         0         0         0         1     0         0    8         0       
 21.  .int00           0         0         0         0         1     0         0    8         0       
 22.  .int01           0         0         0         0         1     0         0    8         0       
 23.  .int02           0         0         0         0         1     0         0    8         0       
 24.  .int03           0         0         0         0         1     0         0    8         0       
 25.  .int04           0         0         0         0         1     0         0    8         0       
 26.  .int05           0         0         0         0         1     0         0    8         0       
 27.  .int06           0         0         0         0         1     0         0    8         0       
 28.  .int07           0         0         0         0         1     0         0    8         0       
 29.  .int08           0         0         0         0         1     0         0    8         0       
 30.  .int09           0         0         0         0         1     0         0    8         0       
 31.  .int10           0         0         0         0         1     0         0    8         0       
 32.  .int11           0         0         0         0         1     0         0    8         0       
 33.  .int12           0         0         0         0         1     0         0    8         0       
 34.  .int13           0         0         0         0         1     0         0    8         0       
 35.  .int14           0         0         0         0         1     0         0    8         0       
 36.  .int15           0         0         0         0         1     0         0    8         0       
 37.  .int16           0         0         0         0         1     0         0    8         0       
 38.  .int17           0         0         0         0         1     0         0    8         0       
 39.  .int18           0         0         0         0         1     0         0    8         0       
 40.  .int19           0         0         0         0         1     0         0    8         0       
 41.  .int20           0         0         0         0         1     0         0    8         0       
 42.  .int21           0         0         0         0         1     0         0    8         0       
 43.  .int22           0         0         0         0         1     0         0    8         0       
 44.  .int23           0         0         0         0         1     0         0    8         0       
 45.  .int24           0         0         0         0         1     0         0    8         0       
 46.  .int25           0         0         0         0         1     0         0    8         0       
 47.  .int26           0         0         0         0         1     0         0    8         0       
 48.  .int27           0         0         0         0         1     0         0    8         0       
 49.  .int28           0         0         0         0         1     0         0    8         0       
 50.  .int29           0         0         0         0         1     0         0    8         0       
 51.  .int30           0         0         0         0         1     0         0    8         0       
 52.  .int31           0         0         0         0         1     0         0    8         0       
 53.  .int32           0         0         0         0         1     0         0    8         0       
 54.  .int33           0         0         0         0         1     0         0    8         0       
 55.  .int34           0         0         0         0         1     0         0    8         0       
 56.  .int35           0         0         0         0         1     0         0    8         0       
 57.  .int36           0         0         0         0         1     0         0    8         0       
 58.  .int37           0         0         0         0         1     0         0    8         0       
 59.  .int38           0         0         0         0         1     0         0    8         0       
 60.  .int39           0         0         0         0         1     0         0    8         0       
 61.  .int40           0         0         0         0         1     0         0    8         0       
 62.  RTC              2         ffd2      ffd2      c4        1     0         0    1         2       
 63.  PORT2            2         ffd4      ffd4      c6        1     0         0    1         2       
 64.  TIMER2_A1        2         ffd6      ffd6      c8        1     0         0    1         2       
 65.  TIMER2_A0        2         ffd8      ffd8      ca        1     0         0    1         2       
 66.  USCI_B1          2         ffda      ffda      cc        1     0         0    1         2       
 67.  USCI_A1          2         ffdc      ffdc      ce        1     0         0    1         2       
 68.  PORT1            2         ffde      ffde      d0        1     0         0    1         2       
 69.  TIMER1_A1        2         ffe0      ffe0      d2        1     0         0    1         2       
 70.  TIMER1_A0        2         ffe2      ffe2      d4        1     0         0    1         2       
 71.  DMA              2         ffe4      ffe4      d6        1     0         0    1         2       
 72.  USB_UBM          2         ffe6      ffe6      d8        1     0         0    1         2       
 73.  TIMER0_A1        2         ffe8      ffe8      da        1     0         0    1         2       
 74.  TIMER0_A0        2         ffea      ffea      dc        1     0         0    1         2       
 75.  ADC12            2         ffec      ffec      de        1     0         0    1         2       
 76.  USCI_B0          2         ffee      ffee      e0        1     0         0    1         2       
 77.  USCI_A0          2         fff0      fff0      e2        1     0         0    1         2       
 78.  WDT              2         fff2      fff2      e4        1     0         0    1         2       
 79.  TIMER0_B1        2         fff4      fff4      e6        1     0         0    1         2       
 80.  TIMER0_B0        2         fff6      fff6      e8        1     0         0    1         2       
 81.  COMP_B           2         fff8      fff8      ea        1     0         0    1         2       
 82.  UNMI             2         fffa      fffa      ec        1     0         0    1         2       
 83.  SYSNMI           2         fffc      fffc      ee        1     0         0    1         2       
 84.  .reset           2         fffe      fffe      f0        2     0         0    1         2       
 85.  .TI.persistent   0         2400      2400      f2        1     0         0    8         268435458
 86.  .debug_info      266       0         0         f2        1     0         0    1         0       
 87.  .debug_info      245       0         0         1fc       1     0         0    1         0       
 88.  .debug_info      247       0         0         2f1       1     0         0    1         0       
 89.  .debug_info      132       0         0         3e8       1     0         0    1         512     
 90.  .debug_line      74        0         0         46c       1     0         0    1         0       
 91.  .debug_line      64        0         0         4b6       1     0         0    1         0       
 92.  .debug_line      64        0         0         4f6       1     0         0    1         0       
 93.  .debug_line      32        0         0         536       1     0         0    1         512     
 94.  .debug_frame     71        0         0         556       1     0         0    1         0       
 95.  .debug_frame     71        0         0         59d       1     0         0    1         0       
 96.  .debug_frame     71        0         0         5e4       1     0         0    1         0       
 97.  .debug_abbrev    84        0         0         62b       1     0         0    1         0       
 98.  .debug_abbrev    80        0         0         67f       1     0         0    1         0       
 99.  .debug_abbrev    80        0         0         6cf       1     0         0    1         0       
100.  .debug_abbrev    31        0         0         71f       1     0         0    1         512     
101.  .debug_str       247       0         0         73e       1     0         0    1         512     
102.  .debug_aranges   32        0         0         835       1     0         0    1         0       
103.  .debug_aranges   32        0         0         855       1     0         0    1         0       
104.  .debug_aranges   32        0         0         875       1     0         0    1         0       
105.  .debug_pubname   27        0         0         895       1     0         0    1         0       
106.  .debug_pubname   29        0         0         8b0       1     0         0    1         0       
107.  .debug_pubname   30        0         0         8cd       1     0         0    1         0       
108.  .debug_pubtype   237       0         0         8eb       1     0         0    1         512     
109.  .debug_info      214       0         0         9d8       1     0         0    1         0       
110.  .debug_info      328       0         0         aae       1     0         0    1         0       
111.  .debug_line      42        0         0         bf6       1     0         0    1         0       
112.  .debug_line      68        0         0         c20       1     0         0    1         0       
113.  .debug_frame     66        0         0         c64       1     0         0    1         0       
114.  .debug_abbrev    41        0         0         ca6       1     0         0    1         0       
115.  .debug_abbrev    88        0         0         ccf       1     0         0    1         0       
116.  .debug_aranges   32        0         0         d27       1     0         0    1         0       
117.  .debug_pubname   29        0         0         d47       1     0         0    1         0       
118.  .debug_pubname   31        0         0         d64       1     0         0    1         0       
119.  .debug_info      475       0         0         d83       1     0         0    1         0       
120.  .debug_info      248       0         0         f5e       1     0         0    1         0       
121.  .debug_info      339       0         0         1056      1     0         0    1         0       
122.  .debug_line      137       0         0         11a9      1     0         0    1         0       
123.  .debug_line      58        0         0         1232      1     0         0    1         0       
124.  .debug_line      74        0         0         126c      1     0         0    1         0       
125.  .debug_frame     71        0         0         12b6      1     0         0    1         0       
126.  .debug_frame     80        0         0         12fd      1     0         0    1         0       
127.  .debug_abbrev    100       0         0         134d      1     0         0    1         0       
128.  .debug_abbrev    69        0         0         13b1      1     0         0    1         0       
129.  .debug_abbrev    140       0         0         13f6      1     0         0    1         0       
130.  .debug_aranges   32        0         0         1482      1     0         0    1         0       
131.  .debug_aranges   32        0         0         14a2      1     0         0    1         0       
132.  .debug_pubname   28        0         0         14c2      1     0         0    1         0       
133.  .debug_pubname   27        0         0         14de      1     0         0    1         0       
134.  .debug_info      217       0         0         14f9      1     0         0    1         0       
135.  .debug_info      240       0         0         15d2      1     0         0    1         0       
136.  .debug_info      236       0         0         16c2      1     0         0    1         0       
137.  .debug_line      32        0         0         17ae      1     0         0    1         0       
138.  .debug_line      48        0         0         17ce      1     0         0    1         0       
139.  .debug_line      48        0         0         17fe      1     0         0    1         0       
140.  .debug_abbrev    51        0         0         182e      1     0         0    1         0       
141.  .debug_abbrev    41        0         0         1861      1     0         0    1         0       
142.  .debug_abbrev    41        0         0         188a      1     0         0    1         0       
143.  .debug_pubname   39        0         0         18b3      1     0         0    1         0       
144.  .debug_pubname   37        0         0         18da      1     0         0    1         0       
145.  .debug_info      236       0         0         18ff      1     0         0    1         0       
146.  .debug_line      60        0         0         19eb      1     0         0    1         0       
147.  .debug_abbrev    40        0         0         1a27      1     0         0    1         0       
148.  .debug_aranges   32        0         0         1a4f      1     0         0    1         0       
149.  .debug_pubname   43        0         0         1a6f      1     0         0    1         0       
150.  .debug_info      273       0         0         1a9a      1     0         0    1         0       
151.  .debug_info      273       0         0         1bab      1     0         0    1         0       
152.  .debug_line      72        0         0         1cbc      1     0         0    1         0       
153.  .debug_line      75        0         0         1d04      1     0         0    1         0       
154.  .debug_abbrev    60        0         0         1d4f      1     0         0    1         0       
155.  .debug_abbrev    60        0         0         1d8b      1     0         0    1         0       
156.  .debug_aranges   32        0         0         1dc7      1     0         0    1         0       
157.  .debug_aranges   32        0         0         1de7      1     0         0    1         0       
158.  .debug_pubname   42        0         0         1e07      1     0         0    1         0       
159.  .debug_pubname   42        0         0         1e31      1     0         0    1         0       
160.  .debug_info      269       0         0         1e5b      1     0         0    1         0       
161.  .debug_line      69        0         0         1f68      1     0         0    1         0       
162.  .debug_abbrev    60        0         0         1fad      1     0         0    1         0       
163.  .debug_aranges   32        0         0         1fe9      1     0         0    1         0       
164.  .debug_pubname   41        0         0         2009      1     0         0    1         0       
165.  .debug_info      275       0         0         2032      1     0         0    1         0       
166.  .debug_info      275       0         0         2145      1     0         0    1         0       
167.  .debug_line      79        0         0         2258      1     0         0    1         0       
168.  .debug_line      79        0         0         22a7      1     0         0    1         0       
169.  .debug_abbrev    60        0         0         22f6      1     0         0    1         0       
170.  .debug_abbrev    60        0         0         2332      1     0         0    1         0       
171.  .debug_aranges   32        0         0         236e      1     0         0    1         0       
172.  .debug_aranges   32        0         0         238e      1     0         0    1         0       
173.  .debug_pubname   43        0         0         23ae      1     0         0    1         0       
174.  .debug_pubname   43        0         0         23d9      1     0         0    1         0       
175.  .debug_info      269       0         0         2404      1     0         0    1         0       
176.  .debug_line      72        0         0         2511      1     0         0    1         0       
177.  .debug_abbrev    60        0         0         2559      1     0         0    1         0       
178.  .debug_aranges   32        0         0         2595      1     0         0    1         0       
179.  .debug_pubname   41        0         0         25b5      1     0         0    1         0       
180.  .debug_info      271       0         0         25de      1     0         0    1         0       
181.  .debug_line      89        0         0         26ed      1     0         0    1         0       
182.  .debug_abbrev    60        0         0         2746      1     0         0    1         0       
183.  .debug_aranges   32        0         0         2782      1     0         0    1         0       
184.  .debug_pubname   42        0         0         27a2      1     0         0    1         0       
185.  .debug_info      297       0         0         27cc      1     0         0    1         0       
186.  .debug_line      62        0         0         28f5      1     0         0    1         0       
187.  .debug_frame     71        0         0         2933      1     0         0    1         0       
188.  .debug_abbrev    85        0         0         297a      1     0         0    1         0       
189.  .debug_aranges   32        0         0         29cf      1     0         0    1         0       
190.  .debug_pubname   39        0         0         29ef      1     0         0    1         0       
191.  .debug_info      318       0         0         2a16      1     0         0    1         0       
192.  .debug_info      213       0         0         2b54      1     0         0    1         0       
193.  .debug_info      217       0         0         2c29      1     0         0    1         0       
194.  .debug_info      326       0         0         2d02      1     0         0    1         0       
195.  .debug_info      314       0         0         2e48      1     0         0    1         0       
196.  .debug_info      260       0         0         2f82      1     0         0    1         0       
197.  .debug_line      32        0         0         3086      1     0         0    1         0       
198.  .debug_line      43        0         0         30a6      1     0         0    1         0       
199.  .debug_line      43        0         0         30d1      1     0         0    1         0       
200.  .debug_line      59        0         0         30fc      1     0         0    1         0       
201.  .debug_line      59        0         0         3137      1     0         0    1         0       
202.  .debug_line      56        0         0         3172      1     0         0    1         0       
203.  .debug_frame     71        0         0         31aa      1     0         0    1         0       
204.  .debug_frame     71        0         0         31f1      1     0         0    1         0       
205.  .debug_frame     71        0         0         3238      1     0         0    1         0       
206.  .debug_abbrev    62        0         0         327f      1     0         0    1         0       
207.  .debug_abbrev    41        0         0         32bd      1     0         0    1         0       
208.  .debug_abbrev    41        0         0         32e6      1     0         0    1         0       
209.  .debug_abbrev    111       0         0         330f      1     0         0    1         0       
210.  .debug_abbrev    111       0         0         337e      1     0         0    1         0       
211.  .debug_abbrev    83        0         0         33ed      1     0         0    1         0       
212.  .debug_aranges   32        0         0         3440      1     0         0    1         0       
213.  .debug_aranges   32        0         0         3460      1     0         0    1         0       
214.  .debug_aranges   32        0         0         3480      1     0         0    1         0       
215.  .debug_pubname   28        0         0         34a0      1     0         0    1         0       
216.  .debug_pubname   30        0         0         34bc      1     0         0    1         0       
217.  .debug_pubname   39        0         0         34da      1     0         0    1         0       
218.  .debug_pubname   37        0         0         3501      1     0         0    1         0       
219.  .debug_pubname   27        0         0         3526      1     0         0    1         0       
220.  .debug_info      446       0         0         3541      1     0         0    1         0       
221.  .debug_info      328       0         0         36ff      1     0         0    1         0       
222.  .debug_info      94        0         0         3847      1     0         0    1         512     
223.  .debug_line      43        0         0         38a5      1     0         0    1         0       
224.  .debug_line      81        0         0         38d0      1     0         0    1         0       
225.  .debug_line      43        0         0         3921      1     0         0    1         512     
226.  .debug_frame     71        0         0         394c      1     0         0    1         0       
227.  .debug_abbrev    162       0         0         3993      1     0         0    1         0       
228.  .debug_abbrev    104       0         0         3a35      1     0         0    1         0       
229.  .debug_abbrev    73        0         0         3a9d      1     0         0    1         512     
230.  .debug_str       183       0         0         3ae6      1     0         0    1         512     
231.  .debug_aranges   32        0         0         3b9d      1     0         0    1         0       
232.  .debug_pubname   33        0         0         3bbd      1     0         0    1         0       
233.  .debug_pubtype   27        0         0         3bde      1     0         0    1         512     
234.  .debug_info      772       0         0         3bf9      1     0         0    1         0       
235.  .debug_info      472       0         0         3efd      1     0         0    1         0       
236.  .debug_info      57        0         0         40d5      1     0         0    1         512     
237.  .debug_info      44        0         0         410e      1     0         0    1         512     
238.  .debug_line      64        0         0         413a      1     0         0    1         0       
239.  .debug_line      148       0         0         417a      1     0         0    1         0       
240.  .debug_line      46        0         0         420e      1     0         0    1         512     
241.  .debug_line      128       0         0         423c      1     0         0    1         512     
242.  .debug_frame     86        0         0         42bc      1     0         0    1         0       
243.  .debug_abbrev    141       0         0         4312      1     0         0    1         0       
244.  .debug_abbrev    112       0         0         439f      1     0         0    1         0       
245.  .debug_abbrev    36        0         0         440f      1     0         0    1         512     
246.  .debug_str       195       0         0         4433      1     0         0    1         512     
247.  .debug_abbrev    36        0         0         44f6      1     0         0    1         512     
248.  .debug_str       262       0         0         451a      1     0         0    1         512     
249.  .debug_aranges   32        0         0         4620      1     0         0    1         0       
250.  .debug_pubname   42        0         0         4640      1     0         0    1         0       
251.  .debug_pubtype   50        0         0         466a      1     0         0    1         512     
252.  .debug_pubtype   31        0         0         469c      1     0         0    1         512     
253.  .text            550       10000     10000     46bc      2     0         0    1         6       
254.  __TI_build_att   132       0         0         48e2      0     0         0    1879048195  0       
255.  .symtab          22560     0         0         4968      0     16        601  2         0       
256.  .mspabi.exidx    0         0         0         a188      1     8         0    1879048193  130     
257.  .rel.text        264       0         0         a188      0     8         253  9         0       
258.  .rel.debug_inf   72        0         0         a290      0     8         86   9         0       
259.  .rel.debug_inf   56        0         0         a2d8      0     8         87   9         0       
260.  .rel.debug_inf   56        0         0         a310      0     8         88   9         0       
261.  .rel.debug_inf   152       0         0         a348      0     8         89   9         0       
262.  .rel.debug_lin   8         0         0         a3e0      0     8         90   9         0       
263.  .rel.debug_lin   8         0         0         a3e8      0     8         91   9         0       
264.  .rel.debug_lin   8         0         0         a3f0      0     8         92   9         0       
265.  .rel.debug_fra   16        0         0         a3f8      0     8         94   9         0       
266.  .rel.debug_fra   16        0         0         a408      0     8         95   9         0       
267.  .rel.debug_fra   16        0         0         a418      0     8         96   9         0       
268.  .rel.debug_ara   16        0         0         a428      0     8         102  9         0       
269.  .rel.debug_ara   16        0         0         a438      0     8         103  9         0       
270.  .rel.debug_ara   16        0         0         a448      0     8         104  9         0       
271.  .rel.debug_pub   8         0         0         a458      0     8         105  9         0       
272.  .rel.debug_pub   8         0         0         a460      0     8         106  9         0       
273.  .rel.debug_pub   8         0         0         a468      0     8         107  9         0       
274.  .rel.debug_pub   8         0         0         a470      0     8         108  9         0       
275.  .rel.text:_isr   40        0         0         a478      0     8         10   9         0       
276.  .rel.reset       8         0         0         a4a0      0     8         84   9         0       
277.  .rel.debug_inf   32        0         0         a4a8      0     8         109  9         0       
278.  .rel.debug_inf   80        0         0         a4c8      0     8         110  9         0       
279.  .rel.debug_lin   8         0         0         a518      0     8         112  9         0       
280.  .rel.debug_fra   16        0         0         a520      0     8         113  9         0       
281.  .rel.debug_ara   16        0         0         a530      0     8         116  9         0       
282.  .rel.debug_pub   8         0         0         a540      0     8         117  9         0       
283.  .rel.debug_pub   8         0         0         a548      0     8         118  9         0       
284.  .rel.debug_inf   32        0         0         a550      0     8         119  9         0       
285.  .rel.debug_inf   48        0         0         a570      0     8         120  9         0       
286.  .rel.debug_inf   112       0         0         a5a0      0     8         121  9         0       
287.  .rel.debug_lin   8         0         0         a610      0     8         123  9         0       
288.  .rel.debug_lin   8         0         0         a618      0     8         124  9         0       
289.  .rel.debug_fra   16        0         0         a620      0     8         125  9         0       
290.  .rel.debug_fra   16        0         0         a630      0     8         126  9         0       
291.  .rel.debug_ara   16        0         0         a640      0     8         130  9         0       
292.  .rel.debug_ara   16        0         0         a650      0     8         131  9         0       
293.  .rel.debug_pub   8         0         0         a660      0     8         132  9         0       
294.  .rel.debug_pub   8         0         0         a668      0     8         133  9         0       
295.  .rel.debug_inf   24        0         0         a670      0     8         134  9         0       
296.  .rel.debug_inf   32        0         0         a688      0     8         135  9         0       
297.  .rel.debug_inf   32        0         0         a6a8      0     8         136  9         0       
298.  .rel.debug_pub   8         0         0         a6c8      0     8         143  9         0       
299.  .rel.debug_pub   8         0         0         a6d0      0     8         144  9         0       
300.  .relRTC          8         0         0         a6d8      0     8         62   9         0       
301.  .relPORT2        8         0         0         a6e0      0     8         63   9         0       
302.  .relTIMER2_A1    8         0         0         a6e8      0     8         64   9         0       
303.  .relTIMER2_A0    8         0         0         a6f0      0     8         65   9         0       
304.  .relUSCI_B1      8         0         0         a6f8      0     8         66   9         0       
305.  .relUSCI_A1      8         0         0         a700      0     8         67   9         0       
306.  .relPORT1        8         0         0         a708      0     8         68   9         0       
307.  .relTIMER1_A1    8         0         0         a710      0     8         69   9         0       
308.  .relTIMER1_A0    8         0         0         a718      0     8         70   9         0       
309.  .relDMA          8         0         0         a720      0     8         71   9         0       
310.  .relUSB_UBM      8         0         0         a728      0     8         72   9         0       
311.  .relTIMER0_A1    8         0         0         a730      0     8         73   9         0       
312.  .relTIMER0_A0    8         0         0         a738      0     8         74   9         0       
313.  .relADC12        8         0         0         a740      0     8         75   9         0       
314.  .relUSCI_B0      8         0         0         a748      0     8         76   9         0       
315.  .relUSCI_A0      8         0         0         a750      0     8         77   9         0       
316.  .relWDT          8         0         0         a758      0     8         78   9         0       
317.  .relTIMER0_B1    8         0         0         a760      0     8         79   9         0       
318.  .relTIMER0_B0    8         0         0         a768      0     8         80   9         0       
319.  .relCOMP_B       8         0         0         a770      0     8         81   9         0       
320.  .relUNMI         8         0         0         a778      0     8         82   9         0       
321.  .relSYSNMI       8         0         0         a780      0     8         83   9         0       
322.  .rel.debug_inf   48        0         0         a788      0     8         145  9         0       
323.  .rel.debug_lin   8         0         0         a7b8      0     8         146  9         0       
324.  .rel.debug_ara   16        0         0         a7c0      0     8         148  9         0       
325.  .rel.debug_pub   8         0         0         a7d0      0     8         149  9         0       
326.  .rel.debug_inf   56        0         0         a7d8      0     8         150  9         0       
327.  .rel.debug_inf   56        0         0         a810      0     8         151  9         0       
328.  .rel.debug_lin   8         0         0         a848      0     8         152  9         0       
329.  .rel.debug_lin   8         0         0         a850      0     8         153  9         0       
330.  .rel.debug_ara   16        0         0         a858      0     8         156  9         0       
331.  .rel.debug_ara   16        0         0         a868      0     8         157  9         0       
332.  .rel.debug_pub   8         0         0         a878      0     8         158  9         0       
333.  .rel.debug_pub   8         0         0         a880      0     8         159  9         0       
334.  .rel.debug_inf   56        0         0         a888      0     8         160  9         0       
335.  .rel.debug_lin   8         0         0         a8c0      0     8         161  9         0       
336.  .rel.debug_ara   16        0         0         a8c8      0     8         163  9         0       
337.  .rel.debug_pub   8         0         0         a8d8      0     8         164  9         0       
338.  .rel.debug_inf   56        0         0         a8e0      0     8         165  9         0       
339.  .rel.debug_inf   56        0         0         a918      0     8         166  9         0       
340.  .rel.debug_lin   8         0         0         a950      0     8         167  9         0       
341.  .rel.debug_lin   8         0         0         a958      0     8         168  9         0       
342.  .rel.debug_ara   16        0         0         a960      0     8         171  9         0       
343.  .rel.debug_ara   16        0         0         a970      0     8         172  9         0       
344.  .rel.debug_pub   8         0         0         a980      0     8         173  9         0       
345.  .rel.debug_pub   8         0         0         a988      0     8         174  9         0       
346.  .rel.debug_inf   56        0         0         a990      0     8         175  9         0       
347.  .rel.debug_lin   8         0         0         a9c8      0     8         176  9         0       
348.  .rel.debug_ara   16        0         0         a9d0      0     8         178  9         0       
349.  .rel.debug_pub   8         0         0         a9e0      0     8         179  9         0       
350.  .rel.debug_inf   56        0         0         a9e8      0     8         180  9         0       
351.  .rel.debug_lin   8         0         0         aa20      0     8         181  9         0       
352.  .rel.debug_ara   16        0         0         aa28      0     8         183  9         0       
353.  .rel.debug_pub   8         0         0         aa38      0     8         184  9         0       
354.  .rel.debug_inf   64        0         0         aa40      0     8         185  9         0       
355.  .rel.debug_lin   8         0         0         aa80      0     8         186  9         0       
356.  .rel.debug_fra   16        0         0         aa88      0     8         187  9         0       
357.  .rel.debug_ara   16        0         0         aa98      0     8         189  9         0       
358.  .rel.debug_pub   8         0         0         aaa8      0     8         190  9         0       
359.  .rel.data        16        0         0         aab0      0     8         6    9         0       
360.  .rel.debug_inf   16        0         0         aac0      0     8         191  9         0       
361.  .rel.debug_inf   32        0         0         aad0      0     8         192  9         0       
362.  .rel.debug_inf   32        0         0         aaf0      0     8         193  9         0       
363.  .rel.debug_inf   72        0         0         ab10      0     8         194  9         0       
364.  .rel.debug_inf   72        0         0         ab58      0     8         195  9         0       
365.  .rel.debug_inf   56        0         0         aba0      0     8         196  9         0       
366.  .rel.debug_lin   8         0         0         abd8      0     8         200  9         0       
367.  .rel.debug_lin   8         0         0         abe0      0     8         201  9         0       
368.  .rel.debug_lin   8         0         0         abe8      0     8         202  9         0       
369.  .rel.debug_fra   16        0         0         abf0      0     8         203  9         0       
370.  .rel.debug_fra   16        0         0         ac00      0     8         204  9         0       
371.  .rel.debug_fra   16        0         0         ac10      0     8         205  9         0       
372.  .rel.debug_ara   16        0         0         ac20      0     8         212  9         0       
373.  .rel.debug_ara   16        0         0         ac30      0     8         213  9         0       
374.  .rel.debug_ara   16        0         0         ac40      0     8         214  9         0       
375.  .rel.debug_pub   8         0         0         ac50      0     8         215  9         0       
376.  .rel.debug_pub   8         0         0         ac58      0     8         216  9         0       
377.  .rel.debug_pub   8         0         0         ac60      0     8         217  9         0       
378.  .rel.debug_pub   8         0         0         ac68      0     8         218  9         0       
379.  .rel.debug_pub   8         0         0         ac70      0     8         219  9         0       
380.  .rela.text       12        0         0         ac78      0     12        253  4         0       
381.  .rel.debug_inf   64        0         0         ac84      0     8         220  9         0       
382.  .rel.debug_inf   80        0         0         acc4      0     8         221  9         0       
383.  .rel.debug_inf   96        0         0         ad14      0     8         222  9         0       
384.  .rel.debug_lin   8         0         0         ad74      0     8         224  9         0       
385.  .rel.debug_fra   16        0         0         ad7c      0     8         226  9         0       
386.  .rel.debug_ara   16        0         0         ad8c      0     8         231  9         0       
387.  .rel.debug_pub   8         0         0         ad9c      0     8         232  9         0       
388.  .rel.debug_pub   8         0         0         ada4      0     8         233  9         0       
389.  .rel.debug_inf   56        0         0         adac      0     8         234  9         0       
390.  .rel.debug_inf   112       0         0         ade4      0     8         235  9         0       
391.  .rel.debug_inf   72        0         0         ae54      0     8         236  9         0       
392.  .rel.debug_inf   56        0         0         ae9c      0     8         237  9         0       
393.  .rel.debug_lin   8         0         0         aed4      0     8         239  9         0       
394.  .rel.debug_fra   16        0         0         aedc      0     8         242  9         0       
395.  .rel.debug_ara   16        0         0         aeec      0     8         249  9         0       
396.  .rel.debug_pub   8         0         0         aefc      0     8         250  9         0       
397.  .rel.debug_pub   8         0         0         af04      0     8         251  9         0       
398.  .rel.debug_pub   8         0         0         af0c      0     8         252  9         0       
399.  .TI.section.fl   26        0         0         af14      0     0         0    2130706437  0       
400.  .strtab          9933      0         0         af2e      0     1         0    3         32      
401.  .shstrtab        1472      0         0         d5fb      0     1         0    3         32      
--------------- ELF SECTION HEADER ---------------
-File closed

Last question, I am creating a software that performs the relocations in-time reading the ELF file from the flash memory. I was told not to use section names to perform the set up of the program, so I am trying to use flags and types. I would like to know what sections must be copied so that I can check what type and flags they use and ensure that other sections don't have the same.

Thank you.

EDIT: I realised that .text:_isr and .text have the same type and flags, however, I don't need the .text:_isr right ? Isn't that for initialization ? How can I know which one is the .text without checking names ?

Apart from that, this is the output if I filter the sections by flags. Only the ones containing flag = 3 or 6 are shown.

 Idx  Name             Size      VMA       LMA       File off  Algn  EntSize   Info Type     Flags
  5.  .bss             0         0         0         94        1     0         0    8        3       
  6.  .data            16        2400      2400      94        2     0         0    1        3       
  9.  .stack           4         43fc      43fc      a4        2     0         0    8        3       
 10.  .text:_isr       32        4400      4400      a4        2     0         0    1        6       
 15.  .init_array      0         0         0         c4        1     0         0    8        3       
253.  .text            550       10000     10000     46bc      2     0         0    1        6   

If I add a type filter I could discard .init_array and I would have a list of all needed sections. Is there any important section missing ?

To filter all the relocation sections I will check that the section referenced in the "info" attribute has flags 6. However, I still have the problem of differentiating the .text:_isr and .text.

  • I cannot reproduce this result.  Please send in your project.  With that project active, select File | Export.  In the dialog that pops up, expand General then choose Archive File.  The rest of it is straightforward.  Attach the .zip file to your next post.

    Thanks and regards,

    -George

  • Here it is. In previous versions I used the Red Hat compiler so there are a lot of folders, plus, I forgot to mention that the project is supposed to generate a relocatable file, so please don't forget to answer the questions in the bottom of the first post if you know the answer.

    Thank you.

    ButtonLed.zip

  • Yes, that look about right in terms of number of sections.  The vast majority of sections are debugging info and relocations, neither of which get allocated to target memory.

    As I noted in the other thread, you must load every section which has section type SHT_PROGBITS and section flag SHF_ALLOC.  More precisely, you must allocate space for every section that is SHF_ALLOC, and you must copy the initial value of each section which has type SHT_PROGBITS.  This includes .init_array, although you could probably get away with not loading .init_array because it has zero size.

    Judging by its name, .text:_isr probably contains the interrupt service routines.  For an arbitrary program, you can't just leave out this section; if it has interrupt service routines, it probably needs them to function correctly.

    If the boot routine does not do what you want, you need to recompile the ELF executable with a boot routine that is more suitable to your system.  The default boot routine provided in the TI RTS (and most custom boot routines for other projects) assume bare metal mode, and your system is clearly not bare metal.  I understand that in a system like Linux, you don't start every program with a bare metal boot routine, but that's because you link every Linux program with a Linux-specific boot routine which understands that is running under Linux.

    You might be able to get away without a special boot routine if the programs you are trying to load are particularly well-behaved, but what you're really trying to do is make a simple operating system, and making this work in the general case is quite complicated.  Other TI compilers provide features (e.g. PIC, dynamic linking) to facilitate concurrent programs, but the TI MSP compiler just doesn't provide these features.

  • I filtered by SHF_ALLOC as you said and this is the output:

    Idx  Name             Size      VMA       LMA       File off  Algn  EntSize   Info Type     Flags
      5.  .bss             0         0         0         94        1     0         0    8        3       
      6.  .data            16        2400      2400      94        2     0         0    1        3       
      9.  .stack           4         43fc      43fc      a4        2     0         0    8        3       
     10.  .text:_isr       32        4400      4400      a4        2     0         0    1        6       
     15.  .init_array      0         0         0         c4        1     0         0    8        3       
     16.  .mspabi.extab    0         0         0         c4        1     0         0    8        2       
     62.  RTC              2         ffd2      ffd2      c4        1     0         0    1        2       
     63.  PORT2            2         ffd4      ffd4      c6        1     0         0    1        2       
     64.  TIMER2_A1        2         ffd6      ffd6      c8        1     0         0    1        2       
     65.  TIMER2_A0        2         ffd8      ffd8      ca        1     0         0    1        2       
     66.  USCI_B1          2         ffda      ffda      cc        1     0         0    1        2       
     67.  USCI_A1          2         ffdc      ffdc      ce        1     0         0    1        2       
     68.  PORT1            2         ffde      ffde      d0        1     0         0    1        2       
     69.  TIMER1_A1        2         ffe0      ffe0      d2        1     0         0    1        2       
     70.  TIMER1_A0        2         ffe2      ffe2      d4        1     0         0    1        2       
     71.  DMA              2         ffe4      ffe4      d6        1     0         0    1        2       
     72.  USB_UBM          2         ffe6      ffe6      d8        1     0         0    1        2       
     73.  TIMER0_A1        2         ffe8      ffe8      da        1     0         0    1        2       
     74.  TIMER0_A0        2         ffea      ffea      dc        1     0         0    1        2       
     75.  ADC12            2         ffec      ffec      de        1     0         0    1        2       
     76.  USCI_B0          2         ffee      ffee      e0        1     0         0    1        2       
     77.  USCI_A0          2         fff0      fff0      e2        1     0         0    1        2       
     78.  WDT              2         fff2      fff2      e4        1     0         0    1        2       
     79.  TIMER0_B1        2         fff4      fff4      e6        1     0         0    1        2       
     80.  TIMER0_B0        2         fff6      fff6      e8        1     0         0    1        2       
     81.  COMP_B           2         fff8      fff8      ea        1     0         0    1        2       
     82.  UNMI             2         fffa      fffa      ec        1     0         0    1        2       
     83.  SYSNMI           2         fffc      fffc      ee        1     0         0    1        2       
     84.  .reset           2         fffe      fffe      f0        2     0         0    1        2       
     85.  .TI.persistent   0         2400      2400      f2        1     0         0    8        268435458
    253.  .text            550       10000     10000     46bc      2     0         0    1        6       
    256.  .mspabi.exidx    0         0         0         a188      1     8         0    1879048193 130     

    As we see, there are a lot of sections here, if we also add the SHT_PROGBITS to the filter, there are still a lot of them, mostly peripheral registers. (1) Any idea how to avoid initializing these ? Checking for size == 0 doesn't work here.

    Regarding .text:_isr, if the program doesn't have interrupts, (2) could this be ignored ?

    I don't understand the concepts boot routine and bare metal mode. (3) Is the boot routine in .text:_isr ? (4) Can I change the boot of a program so that it's empty ? That would make the relocation easier since the board doesn't need to be initialized for every new program loaded.

    I also wanted to point out that I am not developing the OS, however, I have to consider that an OS in the future will load several ELF files so I have to take into account that they may overlap (like initializing Timer registers etc.).

    Thank you.

  • I'm pretty sure those small sections are all slots in the interrupt vector. Note the addresses are all between ffd2 and fffe. They are in fact supposed to be loaded. Per your claim your program does not have interrupts, you could omit these. The only way to tell them apart from the other sections would be by name or address. However, I still recommend that you instead change your linker command file such that you don't have them in the first place.

    Looking at ButtonLED/Debug/ButtonLED.out from an earlier post, it appears that .text:_isr contains only the boot routine. The boot routine is responsible for setting things like the stack pointer, so you really need it. Otherwise, your loader needs to set the stack pointer properly. Please read chapter 2 chapter 3 "Program Loading and Running" of the latest MSP430 Assembly Language Tools User's Guide, which fully defines and describes the boot routine:
    software-dl.ti.com/.../

    I understand that you are not developing the whole OS, but you are developing a part of an OS and you need to be very familiar with how the loaded programs and the loader will co-exist.

    Roughly speaking "bare metal" means there is only one program is running on the chip, and no OS. This program controls everything.

    Yes, you can change the boot routine however much you want. I just don't recommend altering the program at load time.

  • EDIT : After talking to my boss, I was told that the program must work with all types of resources like interrupts, timers... We will just assume the programmer is aware of this and won't use the same resources in several programs, so that they don' overlap. (5) Could you tell me what do I have to take care of in order to achieve this ? I can't load all those sections from ffd2 to fffe because they may erase the previous settings. (6) Would my (3) take care of that by removing it ?

    Archaeologist said:
    I'm pretty sure those small sections are all slots in the interrupt vector

    (1) I don't understand, slots ?

    Archaeologist said:
    They are in fact supposed to be loaded

    But once the Loader is started, I don't have to load them again for every ELF I want to load, (2) right ? I so, I could just take it out from the linker script, (3) right ?

    Archaeologist said:
    It appears that .text:_isr contains only the boot routine. The boot routine is responsible for setting things like the stack pointer, so you really need it

    Okey, just to make sure I got it, I will post here all I think the initialization code is.

    #pragma CLINK(_c_int00_noargs_noexit)
    CSTART_DECL _c_int00_noargs_noexit()
    {
       STACK_INIT();
       if (_system_pre_init() != 0) _auto_init(); // Actually this functions calls the one below, IDK how.
       main(0);
       abort();
    }
    
    void AUTO_INIT_HOLD_WDT(void)
    {
        run_binit();
    
        uint16_t initial_WDT = WDTCTL;
        WDTCTL = HOLD_WDT;
    
        run_cinit();
    
        WDTCTL = RESTORE_WDT(initial_WDT);
    
        run_pinit();
    }


    I asked about ignoring .text:_isr because I think I don't need to execute this for every program I load, (4) do I ?

    Archaeologist said:
    chapter 2 "Program Loading and Running"

    That title is for chapter 3, so I read that one.

  • The interrupt vector table is an array of pointers to interrupt handler functions.  Each element ("slot") in the array/table contains the handler for a specific interrupt.

    Jon Zarate said:
    the program must work with all types of resources like interrupts, timers... We will just assume the programmer is aware of this and won't use the same resources in several programs, so that they don' overlap.

    Then you are defining an API.  You are setting requirements that any programmer who wants to use your loader must follow.  That is, they must compile their programs in a certain way, with either no boot routine or a boot routine which is compatible with your loader.  Additionally, you need some way to coordinate between programs as to which interrupts each will manage; perhaps the program would only contain interrupt vector slots for those interrupts it will handle.  Given that programmers will need to do this, you probably should not further alter the program in the boot loader, so your loader should not be trying to make the decision as to whether to leave out the boot routine or interrupt vector table entries.

    We've gone pretty far with these discussions, I feel I must mention... You're trying to develop a tool well beyond what TI officially supports, and I can't afford to spend this much time helping you with it.  You're dealing with multiple complicated topics. Your project's scope is probably a lot bigger than you anticipate, and the requirements are a bit vague.  You might want to take a step back and seriously consider whether what you are developing is the right way to solve the overarching issue.  There are other strategies for having multiple tasks in a system, including multithreading or SYS/BIOS, and there are compiler features that could be added to the MSP compiler to make things easier, such as PIC or dynamic linking.  I'm also skeptical that your production system will be able to afford the space to store multiple ELF object files in target memory.

  • I eventually realised what the slots were due to the names. Are they used to store the value (address of the function) to jump to in case the interrupt is raised ? You mentioned a handler, I guess it's the code that takes care of changing the PC before and after the interrupt, (1) does it do anything else ?

    I think it's still not decided how the programmer will approach the problem as I am in the first versions yet, but looks like a good solution. Maybe developing a C program that prepares the ELF file would make it fast and easy to achieve.

    Regarding the project: I understand what you're saying. Believe me when I say that I felt the solution was really complex since day 0. Unfortunately, I am a student working on his final degree project and I was told what to do, I did not take part in the solution, I am just researching how to do it. and the fact I never really worked with micro controllers is helping neither That's why I am really grateful for your continuous support.

    I asked about PIC, and looks like it's not good from a security point of view. I read that dynamic linking works with shared libraries so I don't really understand how that could help me since I am not using any (2)

    The RAM problem. It seems that they only need to have a couple of programs running and they plan to buy extra ram space.

    I wanted to add that the goal is related to security. I mean, the whole idea is to add ASLR.

    I will try to keep the questions short and straightforward, but this forum is my only help resource so depending on my issue I may not always succeed. if you can't afford to help just don't do it. I am aware of the complexity of the project, but there is nothing I can do about it.

  • For MSP430 yes, the slots hold a pointer to the interrupt handler, which is a function. One of those handlers is the RESET handler, which is typically the boot routine, so that when the device is RESET, it starts the program again. On interrupt, the MSP CPU handles pushing the return address to the stack and adjusting the PC. See section 1.3.4 "Interrupt Processing" in the MSP430x5xx/MSP430x6xx Family User's Guide SLAU208.

    I'm relieved to hear that this is a research project, that means you don't really have to make it robust for every single contingency, which would be a lot of work. However, it also means you can't wait around for the compiler to add features.