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When is memory barrier instruction needed in TM4C129?

Jong-won Lee
Prodigy 70 points


I read that memory barrier instruction is needed for strong-ordered memory access in ARM Cortex-M documents.

I want to know if memory barrier instruction is needed in TM4C129x processor.

If needed, I want to get some examples in which memory barrier instruction is required. (with specific codes)

Best regards,

  • TI__Guru**** 251760 points

    Jong-won Lee said:
    I read that memory barrier instruction is needed for strong-ordered memory access in ARM Cortex-M documents.

    Please indicate exactly where in the ARM documents you read this.  I'd like to see it in full context.

    Thanks and regards,

    -George