Hello,
It took me a while to figure out why the IRQ associated to a GPIO was not working on my DM6437, so I decided to share my observations just in case someone else is having a similar problem and in hope to have things fixed in a future release of CCS and PSP drivers.
Suppose we need to enable GPIO 75 interrupts (on falling edges) on a DM6437.
According to TMS320DM643x DMP General-Purpose Input/Output (GPIO) User's Guide:
http://focus.ti.com/lit/ug/spru988b/spru988b.pdf
we need to configure Bank 4 interrupt (EN4) in the GPIO interrupt per-bank enable register (BINTEN) and enable falling edge interrupt detection on GPIO pin 75 (SETFAL75 - bit 11) in GPIO Banks 4 and 5 Set Falling Edge Interrupt Register (SET_FAL_TRIG45).
Using the DM6437 Chip Support Register Configuration Macros, the code should be something like:
CSL_GpioRegsOvly gpioRegs = (CSL_GpioRegsOvly)CSL_GPIO_0_REGS;
CSL_FINST(gpioRegs->BINTEN, GPIO_BINTEN_EN4, ENABLE);
CSL_FINST(gpioRegs->SET_FAL_TRIG45, GPIO_SET_FAL_TRIG45_SETFAL11, ENABLE);
But it does not enable IRQ for GPIO75. Looking to the CSLr file:
pspdrivers_1_10_03\packages\ti\sdo\pspdrivers\soc\dm6437\dsp\cslr_gpio.h
We see that we have to set EN5 !!!
CSL_FINST(gpioRegs->BINTEN, GPIO_BINTEN_EN5, ENABLE);
And not to help neither, in CCS version 4.1.2.00027, when showing the bit fields in the register window we would expect to see BITEN EN_4 changing from 0 to 1 but it is EN_2 that changed!!! Similarly, instead of SET_FAL_TRIG45 SETFAL_11, it is SETFAL_20 that changed from 0 to 1!!!
Looking to C:\Program Files\Texas Instruments\ccsv4\common\targetdb\Modules\dm64lc_cslr_gpio_003.xml
we see that all EN_n, DIR_n, OUT_n, CLR_n, IN_n, SETRIS_n, CLRRIS_n, SETFAL_n, CLRFAL_n and STAT_n bitfields are reversed.
It would be interresting to have both XML and CSL files updated.
Best regards,
Galadriel