• Locked Locked
  • Replies 1 reply
  • Subscribers 54 subscribers
  • Views 1070 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Clock cycle count different for same function.

Sureshbabu Ramalingam
Prodigy 100 points


I was trying to figure out clock cycles using two methods (for C64x+ processor environment) :

1) CCSV5.5->Run->Clock->Enable   :  I make sure the cycle count is zero before entering a function and checked it after the function execution is complete. It is 9 * 10^5 cycles.

2) TI DSP BIOS :  I called the function CLK_gethtime(); before and after the function is called as below : start = CLK_gethtime();   Function();  end = CLK_gethtime();  cycles = end - start;  This shows the cycle count  it takes is : 6*10^5 cycles

Can someone explain if I am missing something ?

Thanks,

Suresh

  • TI__Genius 12595 points
    Suresh,
    I can't speak as to why there are differences between the two methods you are using. There is something I want to share with you though.

    Beginning with the C64x+ CPU core and all DSP core generations since then (C674x, C66x), they all have a free-running 64-bit time-stamp counter that runs at the same clock rate as the CPU. There are two CPU registers, TSCL and TSCH, 32-bits each used to access this counter. these are CPU control registers and not memory mapped. To access them, #include <c6x.h> and use the symbols TSCL and TSCH from your C code.

    After reset, the counter is not running. To start it off running, you have to write to TSCL, the value written doesn't matter, it's just the fact that you wrote to it gets it going.

    To read it, since it's in two separate registers, you have to perform two reads, read the TSCL first, then read TSCH. This is important because the upper half of the counter is only latched into TSCH when a read is performed on TSCL. This is done to get a full 64-bit snapshot of the counter when you perform the first read.

    All the details can be found in the CPU and instruction set user guide.

    So what this means is, you can get a 100% accurate cycle count in your code by capturing the TSCL/TSCH before your code then capturing again afterwards and doing a delta.