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C6000 memory model for the C compiler

ReinierC
Expert 2425 points

Dear experts,

I am currently taking a course on compiler construction, in order to get a better understanding of how things are done, I am looking at the C6748 as a reference architecture, mainly because I have worked on it before.

I am currently looking at scheduling memory accesses from C constructs, and looking at the LDB, LDW and LDH instructions for the C6748, which all take 4 clock cycles to complete. So maybe my question is obvious, but how exactly can this always be guaranteed from any part of internal or external memory, whether the memory is either connected through the EMIFA or the mDDR? How does the TI C compiler handle memory access scheduling?

Can you maybe point me to some literature / resources that can explain these topics in more detail and perhaps more in the general processor architecture case?

  • 0
    Expert 1830 points

    ReinierC said:

    I am currently looking at scheduling memory accesses from C constructs, and looking at the LDB, LDW and LDH instructions for the C6748, which all take 4 clock cycles to complete. So maybe my question is obvious, but how exactly can this always be guaranteed from any part of internal and external memory, whether the memory is either connected through the EMIFA or the mDDR?

    By stalling the CPU. Accesses will in fact take longer than 4/(CPU clock) wall time, but logically, with respect to the pipeline, they will appear to take exactly 4 cycles.

    Markus

  • 0 in reply to Markus Moll
    Expert 2425 points
    So the stalling of the CPU for longer memory accesses is then actually a hardware feature of the architecture and the compiler do not really have to know / worry about that?

    From a compiler point of view, what is the minimum information it needs with regards to the memory architecture or the actual memory implementation?
  • 0 in reply to ReinierC
    TI__Guru**** 253380 points

    ReinierC said:
    So the stalling of the CPU for longer memory accesses is then actually a hardware feature of the architecture and the compiler do not really have to know / worry about that?

    Correct.

    ReinierC said:
    From a compiler point of view, what is the minimum information it needs with regards to the memory architecture or the actual memory implementation?

    Nothing.  With regard to correctness, the memory interface is never a concern.  It can be a concern with regard to optimization.

    Thanks and regards,

    -George