Other Parts Discussed in Thread: TM4C1294NCPDT
When using CCS 6.1.3.00033 to check when interrupts were disabled / restored in SYS/BIOS for a Cortex-M4F (TM4C1294NCPDT) noticed that the CCS disassembly view was showing the raw .word value for some instructions rather than the actual instruction:
ti_sysbios_knl_Semaphore_post__E():
00002a10: E92D4190 push.w {r4, r7, r8, lr}
324 hwiKey = Hwi_disable();
00002a14: 2120 movs r1, #0x20
00002a16: F3EF8811 .word 0x8811f3ef
00002a1a: F3818811 .word 0x8811f381
00002a1e: 4916 ldr r1, [pc, #0x58]
00002a20: 680A ldr r2, [r1]
00002a22: 1812 adds r2, r2, r0
00002a24: 6811 ldr r1, [r2]
00002a26: 428A cmp r2, r1
00002a28: D01A beq $C$L93
00002a2a: 4814 ldr r0, [pc, #0x50]
300 Task_module->locked = TRUE;
00002a2c: 2301 movs r3, #1
298 UInt key = Task_module->locked;
00002a2e: 8801 ldrh r1, [r0]
300 Task_module->locked = TRUE;
00002a30: 8003 strh r3, [r0]
59 elem = obj->elem.next;
00002a32: 6810 ldr r0, [r2]
60 next = elem->next;
00002a34: 6804 ldr r4, [r0]
61 obj->elem.next = next;
00002a36: 6014 str r4, [r2]
62 next->prev = &(obj->elem);
00002a38: 6062 str r2, [r4, #4]
353 if (BIOS_clockEnabled && (elem->tpElem.clock != NULL)) {
00002a3a: 68C7 ldr r7, [r0, #0xc]
301 return (key);
00002a3c: 460C mov r4, r1
350 elem->pendState = Semaphore_PendState_POSTED;
00002a3e: 7403 strb r3, [r0, #0x10]
00002a40: B10F cbz r7, #0x2a46
678 obj->active = FALSE;
00002a42: 2100 movs r1, #0
00002a44: 82B9 strh r1, [r7, #0x14]
358 Task_unblockI(elem->tpElem.task, hwiKey);
$C$L92:
00002a46: 6880 ldr r0, [r0, #8]
00002a48: 4641 mov r1, r8
00002a4a: F001F9F9 bl #0x3e40
360 Hwi_restore(hwiKey);
00002a4e: F3888811 .word 0x8811f388
362 Task_restore(tskKey);
00002a52: 4620 mov r0, r4
00002a54: F001FA68 bl #0x3f28
00002a58: E8BD8190 pop.w {r4, r7, r8, pc}
00002a5c: EA4F0808 mov.w r8, r8
327 if (((UInt)sem->mode & 0x1) != 0) { /* if BINARY bit is set */
$C$L93:
00002a60: 7A01 ldrb r1, [r0, #8]
00002a62: 0849 lsrs r1, r1, #1
00002a64: BF3A itte lo
331 sem->count++;
00002a66: 8941 ldrh r1, [r0, #0xa]
00002a68: 1C49 adds r1, r1, #1
328 sem->count = 1;
00002a6a: 2101 movs r1, #1
00002a6c: 8141 strh r1, [r0, #0xa]
335 Hwi_restore(hwiKey);
00002a6e: F3888811 .word 0x8811f388
00002a72: E8BD8190 pop.w {r4, r7, r8, pc}
00002a76: 46C0 mov r8, r8
$C$CON109:
00002a78: 674C str r4, [r1, #0x74]
00002a7a: 0000 movs r0, r0
$C$CON110:
00002a7c: 15F8 asrs r0, r7, #0x17
00002a7e: 2000 movs r0, #0
Changing the Disassembly Style from "Mixed ARM/Thumb" to "Thumb Only" didn't correct the disassembly (the Cortex-M4F only supports Thumb mode instructions).
The armdis program from TI ARM compiler v_15.12.1.LTS can disassemble all the instructions, which shows that the instructions CCS failed to disassemble manipulate the BASEPRI register:
002a10: ti_sysbios_knl_Semaphore_post__E:
002a10: .thumb
002a10: .text:ti_sysbios_knl_Semaphore_post__E:
002a10: 2DE99041 STMDB.W R13!, {R4, R7, R8, R14}
002a14: 2021 MOVS R1, #32
002a16: EFF31188 MRS.W R8, BASEPRI
002a1a: 81F31188 MSR.W BASEPRI, R1
002a1e: 1649 LDR R1, $C$CON109 [0x2a78]
002a20: 0A68 LDR R2, [R1]
002a22: 1218 ADDS R2, R2, R0
002a24: 1168 LDR R1, [R2]
002a26: 8A42 CMP R2, R1
002a28: 1AD0 BEQ 0x00002A60
002a2a: 1448 LDR R0, $C$CON110 [0x2a7c]
002a2c: 0123 MOVS R3, #1
002a2e: 0188 LDRH R1, [R0]
002a30: 0380 STRH R3, [R0]
002a32: 1068 LDR R0, [R2]
002a34: 0468 LDR R4, [R0]
002a36: 1460 STR R4, [R2]
002a38: 6260 STR R2, [R4, #4]
002a3a: C768 LDR R7, [R0, #12]
002a3c: 0C46 MOV R4, R1
002a3e: 0374 STRB R3, [R0, #16]
002a40: 0FB1 CBZ R7, 0x00002A46
002a42: 0021 MOVS R1, #0
002a44: B982 STRH R1, [R7, #20]
002a46: $C$L92:
002a46: 8068 LDR R0, [R0, #8]
002a48: 4146 MOV R1, R8
002a4a: 01F0F9F9 BL 0x00003E40
002a4e: 88F31188 MSR.W BASEPRI, R8
002a52: 2046 MOV R0, R4
002a54: 01F068FA BL 0x00003F28
002a58: BDE89081 LDMIA.W R13!, {R4, R7, R8, PC}
002a5c: 4FEA0808 MOV.W R8, R8
002a60: $C$L93:
002a60: 017A LDRB R1, [R0, #8]
002a62: 4908 LSRS R1, R1, #1
002a64: 3ABF ITTE CC
002a66: 4189 LDRHCC R1, [R0, #10]
002a68: 491C ADDCC R1, R1, #1
002a6a: 0121 MOVCS R1, #1
002a6c: 4181 STRH R1, [R0, #10]
002a6e: 88F31188 MSR.W BASEPRI, R8
002a72: BDE89081 LDMIA.W R13!, {R4, R7, R8, PC}
002a76: C046 MOV R8, R8
002a78: $d:
002a78: $C$CON109:
002a78: 4C67 .half 0x674C
002a7a: 0000 .half 0x0000
002a7c: $C$CON110:
002a7c: F815 .half 0x15F8
002a7e: 0020 .half 0x2000
