Other Parts Discussed in Thread: AM3359
Hi All
I've got BBB debug setup with CCS 6.1.3 and xds100v2 blackhawk. I am trying to start linux debugging. I've selected BeagleBone Black as my device during target configuration.
BBB boots up through the sdcard and I stop it at U boot command prompt. I load kernel binary, .dtb through tftp and my rfs is on NFS.
But when I load the vmlinux symbols and let the jtag run, I get below errors, even though the target configuration 'Test Connection' passes:
CortxA8: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0) CortxA8: Trouble Halting Target CPU: (Error -2064 @ 0x0) Unable to read device status. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0)
Below are the complete error logs and the target configuration 'Test Connection' pass logs.
CortxA8: Output: **** AM335x BeagleBlack Initialization is in progress .......... CortxA8: Output: **** AM335x ALL PLL Config for OPP == OPP100 is in progress ......... CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 24MHz CortxA8: Output: **** Going to Bypass... CortxA8: Output: **** Bypassed, changing values... CortxA8: Output: **** Locking ARM PLL CortxA8: Output: **** Core Bypassed CortxA8: Output: **** Now locking Core... CortxA8: Output: **** Core locked CortxA8: Output: **** DDR DPLL Bypassed CortxA8: Output: **** DDR DPLL Locked CortxA8: Output: **** PER DPLL Bypassed CortxA8: Output: **** PER DPLL Locked CortxA8: Output: **** DISP PLL Config is in progress .......... CortxA8: Output: **** DISP PLL Config is DONE .......... CortxA8: Output: **** AM335x ALL ADPLL Config for OPP == OPP100 is Done ......... CortxA8: Output: **** AM335x DDR3 EMIF and PHY configuration is in progress......... CortxA8: Output: EMIF PRCM is in progress ....... CortxA8: Output: EMIF PRCM Done CortxA8: Output: DDR PHY Configuration in progress CortxA8: Output: Waiting for VTP Ready ....... CortxA8: Output: VTP is Ready! CortxA8: Output: DDR PHY CMD0 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD1 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD2 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA0 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA1 Register configuration is in progress ....... CortxA8: Output: Setting IO control registers....... CortxA8: Output: EMIF Timing register configuration is in progress ....... CortxA8: Output: EMIF Timing register configuration is done ....... CortxA8: Output: PHY is READY!! CortxA8: Output: DDR PHY Configuration done CortxA8: Output: **** AM335x BeagleBlack Initialization is Done ****************** CortxA8: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0) CortxA8: Trouble Halting Target CPU: (Error -2064 @ 0x0) Unable to read device status. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0) CortxA8: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0) CortxA8: Trouble Halting Target CPU: (Error -2064 @ 0x0) Unable to read device status. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0) CortxA8: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0)
Below are the Test Connection" logs:
[Start: Texas Instruments XDS100v2 USB Debug Probe_0] Execute the command: %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity [Result] -----[Print the board config pathname(s)]------------------------------------ /home/rohit/.ti/ti/0/0/BrdDat/testBoard.dat -----[Print the reset-command software log-file]----------------------------- This utility has selected a 100- or 510-class product. This utility will load the adapter 'libjioserdesusb.so'. The library build date was 'Apr 8 2016'. The library build time was '02:34:10'. The library package version is '6.0.222.0'. The library component version is '35.35.0.0'. The controller does not use a programmable FPGA. The controller has a version number of '4' (0x00000004). The controller has an insertion length of '0' (0x00000000). This utility will attempt to reset the controller. This utility has successfully reset the controller. -----[Print the reset-command hardware log-file]----------------------------- The scan-path will be reset by toggling the JTAG TRST signal. The controller is the FTDI FT2232 with USB interface. The link from controller to target is direct (without cable). The software is configured for FTDI FT2232 features. The controller cannot monitor the value on the EMU[0] pin. The controller cannot monitor the value on the EMU[1] pin. The controller cannot control the timing on output pins. The controller cannot control the timing on input pins. The scan-path link-delay has been set to exactly '0' (0x0000). -----[The log-file for the JTAG TCLK output generated from the PLL]---------- There is no hardware for programming the JTAG TCLK frequency. -----[Measure the source and frequency of the final JTAG TCLKR input]-------- There is no hardware for measuring the JTAG TCLK frequency. -----[Perform the standard path-length test on the JTAG IR and DR]----------- This path-length test uses blocks of 64 32-bit words. The test for the JTAG IR instruction path-length succeeded. The JTAG IR instruction path-length is 6 bits. The test for the JTAG DR bypass path-length succeeded. The JTAG DR bypass path-length is 1 bits. -----[Perform the Integrity scan-test on the JTAG IR]------------------------ This test will use blocks of 64 32-bit words. This test will be applied just once. Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly. The JTAG IR Integrity scan-test has succeeded. -----[Perform the Integrity scan-test on the JTAG DR]------------------------ This test will use blocks of 64 32-bit words. This test will be applied just once. Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly. The JTAG DR Integrity scan-test has succeeded. [End: Texas Instruments XDS100v2 USB Debug Probe_0]
Please help me rectify this.
