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CacheTune

Andrew52370
Prodigy 20 points

Other Parts Discussed in Thread: CCSTUDIO

Hi,

I'm using CCS, version 3.3.38.2/BIOS 5.31.02/Code Gen Tools v6.0.8.

With Compiler options: -k -o3 -fr"$(Proj_dir)\Debug" -i"C:\CCStudio_v3.3\MyProjects\fest\freq_est_tuned\Debug" -d"_DEBUG" -mt -mw -mv6400

Linker options: -c -m".\Debug\freq_est.map" -o".\Debug\freq_est.out" -w -x -i"C:\CCStudio_v3.3\c6400\mthlib\lib" -l"fastrts64x.lib"

I have a design doing chain processing (FIRs among others) on some big packets. It works, and all my 20 loops

are otimized. Did profiling and everything looks OK. I'm using L2 Cache (128k) configured in DSP/BIOS.

When I ran CacheTune & Profile Viewer I get L1D stall cycles 40%. Most of them are  L1D. miss.write (95%).

For example for a fir filter I read two linear arrays (data[ ] & coef[ ] ) and write to an output y[ ] array. Looking  in the

CacheTune graph in all the reads I have only compulsory misses; but all my writes misses every access.

With L2 Cache 4-way why I don't get in all my writes just compulsory misses?

All my loops have this problem when writing to arrays (SDRAM simple/linear arrays). I don't get on these writes any hit.

Thanks,

Andrew

 

  • 0
    TI__Guru**** 482651 points

    Hi Andrew,

    CacheTune is no longer supported. There were various issues and I'd recommend to stop using it.

    ki

  • 0
    TI__Mastermind 18130 points

    Andrew,

    The L1D is a 2-way read-allocate cache meaning that something is only cached when it is read. When you write out to a variable which was never read in by the CPU it therefore writes directly to the L2. I think this is why you're experiencing constant misses with your writes.

    The TTO organization has done some good work with their training material you may want to check out. Look at module 10 on cache in the BIOS workshop training material. In particular, slides 15 and 31 should be helpful.