The hardware engineer can manually configure the JTAG chain on our board, using zero ohm resistors, so that only the three 6467 devices are in the chain. I setup a target config and I was able to connect to each of the three 6467s, one at a time.
Then he configured the board so that the three 6467s, PROM, and FPGA are all in the chain (similar to the series topology shown in http://processors.wiki.ti.com/index.php/Adaptive_Clocking, except the last two devices don't have RTCK output so the RTCK from last 6467 goes back to JTAG connector). The SdConfigEx tool gives an error when I do Emulator->Test, so there is something wrong with the chain. So, he disconnected RTCK output of the last 6467 from TCK the input of the PROM (6467 RTCK output still connects to the RTCK of the JTAG connector). And connected TCK from the JTAG connector directly to the PROM. Then, the SdConfigEx is successful and says there are 5 devices with an IR of 44, which is correct. However, when I create a 5 device target config and try to connect to the first 6467, I get "Unable to determine target endian mode" (error 0x80000240/-1159).
It is not clear how to connect the RTCK signal if the last two devices do not have RTCK output. Are we even allowed to mix adaptive clocking and non-adaptive clocking devices in the same chain?