An issue came up after recompiling aeons old code with some minor changes in pin assignment. The issue is that the wrong data location is written to due to DP Load Optimization.
In the code below, some members of a structure (sysvar) are being initialized with constants. The structure only contains constants and is located in “RAML” (0x8000 – 0xA000). The first 2 assignment work correctly. The DP is assigned initially to the range 0x8E40 – 0x8E7F. The structure starts at 0x8E7C, so the first 2 members will be accessible with the set DP range. For consecutive access, the DP range should be incremented….but it is not. Instead, the DP pointer offset is looped around and memory before the actual structure gets modified…at 0x8E40.
Please refer to the attached document for more information. This is very strange and I have never seen anything like it which makes it a bit scary...
- Dirk
