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Simple Register Examination - OMAP using XDS100V2

Tim52767
Prodigy 20 points

Hi Folks,

1st posting here...

I've got a small OMAP 3530 design with new PCBs, and it doesn't work!

Now, I am trying to do some basic de-bugging & want to look at the OMAPs registers.

I downloaded CCS4, and have attached a XDS100V2 and done the emulator selection and processor selection.

Is there a simple tutorial or explanation of how I can start looking at the registers (without having an actual project to compile/download/debug?

 

Thanks! 

Tim

  • 0
    TI__Expert 4995 points

    You probably need to start http://processors.wiki.ti.com/index.php/CCSv4_Getting_Started_Guide and focus on getting your target configuration setup properly and then just doing a connect on the A8 and choosing view registers.

  • 0 in reply to Steve2181
    TI__Guru**** 171819 points

    Tim,

    Just complementing Steve's reply, follow the procedure to configure your board at the section Debugging_Projects and connect to the A8 following the steps 1 through 4 of the section Connecting_to_slave_cores_in_SoC_devices

    Hope this helps,

    Rafael

  • 0 in reply to desouza
    Prodigy 20 points

    Hi All,

    This board is pretty much a 'Beagleboard' lookalike.  I have removed the serial port, and did a few changes to the USB circuitry, but except for the changes, the schematics were identical, and the Allegro layout was pretty similar as well.

    A few more pointers to the below error messages would be most appreciative!

    Thx, Tim

    I went  through the setup of the target Configuration, then I did a right click to launch it, and after a few 'positive' messages, it got an error message:

    Cortex_A8_0: GEL Output: OMAP 32K Watchdog Timer is disable

    Cortex_A8_0: GEL Output: Putting DPLL into bypass before proceeding

    Cortex_A8_0: GEL Output: Putting CORE DPLL into bypass before proceeding

    Cortex_A8_0: GEL Output: Locking CORE DPLL

    Cortex_A8_0: GEL Output: PRCM clock configuration IIA setup has been completed

    Cortex_A8_0: GEL Output: SystemClock = 19.2 MHz

    Cortex_A8_0: GEL Output: DPLL_MULT_VALUE = 242

    Cortex_A8_0: GEL Output: DPLL_DIV_VALUE = 13

    Cortex_A8_0: GEL Output: CORE_DPLL_CLK = 663.771 MHz

    Cortex_A8_0: GEL Output: CORE_CLK = 331.8855 MHz

    Cortex_A8_0: GEL Output: L3_CLK = 165.9427 MHz

    Cortex_A8_0: GEL Output: MM01: mDDR Samsung K4X51323PC - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks

    Cortex_A8_0: GEL Output: common_sdram_init() completed

    Cortex_A8_0: GEL Output: SDRC initilization for mDDR_Samsung_K4X51323PC completed

    Cortex_A8_0: GEL Output: 19.2MHz clock configuration IIa

    Cortex_A8_0: GEL Output: CORTEXA8_CORE_VERSION = 0x411FC083

    Cortex_A8_0: GEL Output: CORE_REVISION = 0x00100003

    Cortex_A8_0: GEL Output: IS NOT COMPREHENDED BY THIS GEL FILE

    Cortex_A8_0: Trouble Reading Register ETM_ID: Error 0x80002004/-1203 Fatal Error during: Register, Control, The DAP access, address 0x000001E4, has returned a SLAVE error.

    Cortex_A8_0: The GEL callback "OnTargetConnect()" is no longer running atomically

    Cortex_A8_0: GEL: Error while executing OnResetDetected(): target is not connected.