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ARM Compilers - TI's ARM Compiler and bitbanding in the Cortex-M3

This question is a bit esoteric in nature but it was mentioned recently and I thought it might be an interesting post.

The Cortex M3 supports bitbanding...previous ARM architectures (ARM9) did not. 

The question is generally speaking how transparent is the bitbanding feature being taken advantage of by the compiler.

Obviously the answers are "it depends on" coding style, amount of access to registers/memory locations supported by bitbanding etc.

Q1:   Does the TI (or any other compiler for Cortex) M3 know how to take advantage of Bitbanding?

Q2:   if my legacy code was optimized for ARM9, then when I recompile, is there a "trick' to get the Bitbanding optimization for M3?

Q3:  Although unlikely, the scenario could also work the opposite direction...C code targeted for M3 would be recompiled for ARM9...what would be

the impact to code efficiency?

 

  • Regarding question 1, a google search leads to this article.  The TI ARM 4.6.3 compiler with that test case with the shell options:

    cl470 -mv7M3 -k bitband.c -o

    generates the same code as described in the article:


    ;*****************************************************************************
    ;* FUNCTION NAME: main                                                       *
    ;*                                                                           *
    ;*   Regs Modified     : A1,A2,SR                                            *
    ;*   Regs Used         : A1,A2,SR                                            *
    ;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                   *
    ;*****************************************************************************
    _main:
    ;* --------------------------------------------------------------------------*
            LDR       A1, $C$CON1           ; |20|
            MOVS      A2, #1                ; |20|
            STR       A2, [A1, #0]          ; |20|
            LDR       A2, [A1, #28]         ; |21|
            LDR       A1, $C$CON2           ; |22|
            STRB      A2, [A1, #0]          ; |22|
            LDRB      A1, [A1, #28]         ; |23|
            BX        LR
            ; BRANCH OCCURS {LR}
    ;******************************************************************************
    ;* CONSTANT TABLE                                                             *
    ;******************************************************************************
            .sect   ".text"
            .align  4
    ||$C$CON1||:    .field  570949632,32
            .align  4
    ||$C$CON2||:    .field  1107820544,32