CCS/MSP430FR5969: Printf causes a breakpoint

I had a minute to look at this. The problem is "caused" by setting an FRAM waitstate in clock init. 

If you have 16MHz DCO and waitstate=1, you get spurious breakpoint.

If you have 8MHz DCO and waitstate=1, you get a spurious breakpoint.

If you have 8MHz DCO and waitstate=0, spurious breakpoint goes away. 

8MHz DCO + waitstate = 2 => spurious breakpoint and so on. 

Just changing that FRAM waitstate from 0 to 1 makes problem appear in this snippet,  

CSCTL1 = DCOFSEL_3 | DCORSEL; // Set DCO to 16MHz

line actually sets the clock to 8MHz, DCOFSEL_4 sets it to 16MHz. We can't obviously have 0 FRAM waitstate with 16MHz however. 

/* Setup clocks with kludges a plenty 16MHz MCLK 1MHz SMCLK */
void Init_Clock(){
	//FRAM needs a wait state for 16MHz

	FRAMCtl_configureWaitStateControl(FRAMCTL_ACCESS_TIME_CYCLES_0);
	/* Initclocksignal crashes the processor @ 16MHz so we have to use registers the hard way..
	 * SMCLK 16MHZ / 16 = 1MHz
    */

	CS_initClockSignal(CS_MCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1);
    //Set SMCLK = DCO with frequency divider of 16 = 1MHz
    CS_initClockSignal(CS_SMCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_16);

	/* DCO 16MHz clock workaround code*/
	uint16_t tempCSCTL3 = 0;

	CSCTL0_H = CSKEY_H; // Unlock CS registers
	// Assuming SMCLK and MCLK are sourced from DCO
	// Store CSCTL3 settings to recover later
	tempCSCTL3 = CSCTL3;
	/* Keep overshoot transient within specification by setting clk sources
	to divide by 4*/
	// Clear the DIVS & DIVM masks (~0x77)and set both fields to 4 divider
	CSCTL3 = CSCTL3 & (~(0x77)) | DIVS__4 | DIVM__4;
	CSCTL1 = DCOFSEL_3 | DCORSEL; // Set DCO to 16MHz
	/* Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer +
	(10us / (1/4MHz))*/

	__delay_cycles(0x60);
	CSCTL3 = tempCSCTL3; // Set all dividers
	CSCTL0_H = 0; // Lock CS registers
	printf("foo!\n");
}