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CCS/TMS320C6678: Discrepancy between DDR3 EMIF Memory Control Registers viewer, and Memory Browser

Alvaro Garay
Prodigy 220 points
Part Number: TMS320C6678

Tool/software: Code Composer Studio

There is a discrepancy between DDR3 EMIF Memory Control Registers viewer, and Memory Browser, but for the other registers it looks fine. For example, the MSMC and HYPERLINK registers between DDR3 EMIF register are good. 

I'm running CCv6 version: 6.2.0.00050

C6678.xml file shows the correct starting base address.

 <instance href="../Modules/Keystone/ddr_emif.xml" id="DDR3" xml="ddr_emif.xml" xmlpath="../Modules/Keystone/" HW_version="TMS320C6678" description="DDR3 EMIF memory controller configuration (DDR3)" requestor="TMS320C6678" baseaddr="0x21000000" endaddr="0x210001FF" size="0x0200" accessnumbytes="4" permissions="p" />

  • 0
    TI__Guru**** 171004 points
    Hi,

    Thanks for reporting this.

    The discrepancy between the two is due to the fact the Registers view shows the address in Physical memory space, while your Memory Browser is configured to show it from a CPU perspective. The detailed explanation is shown in the thread below:
    e2e.ti.com/.../151934

    Therefore, the ultimate fix is to adjust the addresses in the device XML file - I sent this thread to the appropriate groups to comment further on the schedules for this to be fixed.

    I apologize for the inconvenience,
    Rafael
  • 0 in reply to desouza
    Prodigy 220 points
    Hi Desouza,

    The information you have provided was a good introduction. I modified the xml file successfully by making the base address to 36 bits.

    I appreciate you are taking action to fix this issue with your teams.

    - evmc6678l.gel -> xmc_setup() maps the ddr emif registers <C:\ti\ccsv6\ccs_base\emulation\boards\evmc6678l\gel>
    - C6678.xml needs edit to fix issue when using gel above <C:\ti\ccsv6\ccs_base\common\targetdb\devices>

    Best,
    Alvaro