This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS: What is "Other Stalls Total" in "Stall Cycle Profiler"

Tool/software: Code Composer Studio

Hello,

I profiled C66 with hardware trace analyzer's "stall profile" and "Other Stalls Total" was big in result. 

What can cause "Other Stall" and how to reduce it? Core is C66 in TDA2x.

Best regards,

Wilson.

  • Wilson,

    Please apologize for the delay.

    It is hard to tell what could be causing "other stalls", given this falls outside of the visibility of the Trace HW circuit inside the device.

    I would, however, set up a Stall Profiling job and try to set the Trace Range to specific points where there is a higher possibility of stalls due to external memory access or peripheral/port accesses - these areas are usually the ones that suffer the most. It is an investigative job, as you will have to test several areas of your code, but it may be worth to understand where the optimization can be applied.

    For details you can check the CCS Help and search for "Trace Stall" - there are some good references there.

    I will think of any additional scenarios and report back to this thread.

    Hope this helps,
    Rafael
  • Rafael,

    Thanks for guiding. 

    Does "external memory access" mean L2 miss? Or access to non-cache region?

    EDMA PARAM writing is also peripheral access? 

    Thanks & regards,

    Wilson.

  • Wilson,

    user4836286 said:
    Does "external memory access" mean L2 miss? Or access to non-cache region?

    Stalls on external memory access can be related to anything that causes the CPU to wait for a response to a data access. I looked at the Advanced Settings of the Stall Profiling for the C66x core of a similar device to the TDA2x and found out the hardware does not flag L2 misses, thus the tool is unable to differentiate between the two scenarios.

    user4836286 said:
    EDMA PARAM writing is also peripheral access? 

    By expanding the Advanced settings you can try to track down DMA conflicts in L1D memory, but I suspect EDMA is not monitored by this parameter (I am not a device expert). 

    In any case, I will try to search for additional ways to monitor information at L2 and peripheral level and see what I can find. I will report back to this thread in case I find anything relevant.

    Hope this helps,

    Rafael

  • Rafael,
    Thanks for clarifying. I'll make another thread if I need more details.
    Best regards,
    Wilson.