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Compiler/TMS320F28379D: Different RAM Footprint on CPU1 and CPU2 although using same #pragma DATASECTION("xxxx") orders

user4221161
Expert 1050 points
Part Number: TMS320F28379D
Other Parts Discussed in Thread: LAUNCHXL-F28379D

Tool/software: TI C/C++ Compiler

Hello there, 

i have started to use the LAUNCHXL-F28379D. 
The concept is to have all "IO things" on CPU1 while having all the algorithm on CPU2.
So the idea is to place all ADC results and all the other stuff in arrays which are then tied to global shared ram with a #pragma DATASECTION.
Of course the code in the main.cpp files of ech project are a bit different, but the #pragma DATASECTON´s are in the same order.
I have investgated the .map file and actually the arrays on the CPU´s don´t have the same order, see attachments at the bottom (mapfile, cmd files, pragma SECTIONS).
The projects are both running on optimization level -O2, have also tried the "off" condition with same result.
My question is how can i make sure the arrays are arranges equally on both CPU´s map files?
One idea could be to scramble the Global Shared RAM in chunks exactly the size of each array and define a name in the SECTION area of the map file. But this would mean some typing efford and more important a higher risk to forget something, whan an array gets changed in size...
Are there other approaches than that?

best regards, 
Jasson


Fullscreen CPU_0_PRAGMAS.txt Download 
#ifdef USE_ADC
    ADC_Source* adcSptr;

	#pragma DATA_SECTION("SHARERAMGS0");
	Uint16 adc_U[AMT_OF_ALL_ADC_VALS/2];

	#pragma DATA_SECTION("SHARERAMGS0");
	Uint16 adc_I[AMT_OF_ALL_ADC_VALS/2];
#endif
#ifdef USE_DAC
	DACSink* dacSptr;

		#pragma DATA_SECTION("SHARERAMGS0");
		Uint16 i_Set[(AMT_OF_ONEP_SYS + (AMT_OF_THRP_SYS*3))/2];

		#pragma DATA_SECTION("SHARERAMGS0");
		Uint16 i_Band[(AMT_OF_ONEP_SYS + (AMT_OF_THRP_SYS*3))/2];
#endif

#ifdef USE_PWM
		#pragma DATA_SECTION("SHARERAMGS0");
		volatile Uint32* pwmArr[10];
#endif

#ifdef USE_IOEXP_NONISO
		IO_Expander *ioE;
		unsigned char* portPtrOutNonIso;
		unsigned char* portPtrInNonIso;
		#pragma DATA_SECTION("SHARERAMGS0");
		unsigned char ioExpNonIsoOutArr[5];

		#pragma DATA_SECTION("SHARERAMGS0");
		unsigned char ioExpNonIsoInArr[5];
#endif

#ifdef USE_IOEXP_ISO
		IO_Expander *ioEIso;
		unsigned char* portPtrOutIso;
		unsigned char* portPtrInIso;
		#pragma DATA_SECTION("SHARERAMGS0");
		unsigned char ioExpIsoOutArr[5];

		#pragma DATA_SECTION("SHARERAMGS0");
		unsigned char ioExpIsoInArr[5];
#endif

#ifdef USE_EXT_10b_ADC
		EXT_ADC* ext10bAdcPtr;
		#pragma DATA_SECTION("SHARERAMGS0");
		Uint16 ext10bAdcVals[8];
#endif

#ifdef USE_EXT_8b_ADC
		EXT_ADC_MAX11605* extAdc11605Ptr;
		#pragma DATA_SECTION("SHARERAMGS0");
		unsigned char extAdc_11605_Vals[8];
#endif

Fullscreen CPU_1_PRAGMAS.txt Download 
#ifdef USE_ADC
	#pragma DATA_SECTION("SHARERAMGS0");
	Uint16 adc_U[AMT_OF_ALL_ADC_VALS/2];

	#pragma DATA_SECTION("SHARERAMGS0");
	Uint16 adc_I[AMT_OF_ALL_ADC_VALS/2];
#endif
#ifdef USE_DAC
		#pragma DATA_SECTION("SHARERAMGS0");
		Uint16 i_Set[(AMT_OF_ONEP_SYS + (AMT_OF_THRP_SYS*3))/2];

		#pragma DATA_SECTION("SHARERAMGS0");
		Uint16 i_Band[(AMT_OF_ONEP_SYS + (AMT_OF_THRP_SYS*3))/2];
#endif

#ifdef USE_PWM
		#pragma DATA_SECTION("SHARERAMGS0");
		volatile Uint32* pwmArr[10];
#endif

#ifdef USE_IOEXP_NONISO
		#pragma DATA_SECTION("SHARERAMGS0");
		unsigned char ioExpNonIsoOutArr[5];

		#pragma DATA_SECTION("SHARERAMGS0");
		unsigned char ioExpNonIsoInArr[5];
#endif

#ifdef USE_IOEXP_ISO
		#pragma DATA_SECTION("SHARERAMGS0");
		unsigned char ioExpIsoOutArr[5];

		#pragma DATA_SECTION("SHARERAMGS0");
		unsigned char ioExpIsoInArr[5];
#endif

#ifdef USE_EXT_10b_ADC
		#pragma DATA_SECTION("SHARERAMGS0");
		Uint16 ext10bAdcVals[8];
#endif

#ifdef USE_EXT_8b_ADC
		#pragma DATA_SECTION("SHARERAMGS0");
		unsigned char extAdc_11605_Vals[8];
#endif

Fullscreen CPU_0_CMD.txt Download 
MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000
   RAMGS15          : origin = 0x01B000, length = 0x001000
   RESET           	: origin = 0x3FFFC0, length = 0x000002
   
   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */   

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   RAMGS11     : origin = 0x017000, length = 0x001000
   RAMGS12     : origin = 0x018000, length = 0x001000
   RAMGS13     : origin = 0x019000, length = 0x001000

   
   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
}


SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)

#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} LOAD = FLASHD,
                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)
   #endif
#endif
						 
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1        PAGE = 1
   .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
   .esysmem            : > RAMLS5       PAGE = 1

   /* Initalized sections go in Flash */
   .econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
   
   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
   
   SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   
   /* The following section definitions are required when using the IPC API Drivers */ 
    GROUP : > CPU1TOCPU2RAM, PAGE = 1 
    {
        PUTBUFFER 
        PUTWRITEIDX 
        GETREADIDX 
    }
    
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }  
    
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Fullscreen CPU_1_CMD.txt Download 
MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000
   RAMGS15          : origin = 0x01B000, length = 0x001000
   RESET           	: origin = 0x3FFFC0, length = 0x000002
   
   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */   

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   RAMGS11     : origin = 0x017000, length = 0x001000
   RAMGS12     : origin = 0x018000, length = 0x001000
   RAMGS13     : origin = 0x019000, length = 0x001000

   
   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
}


SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)

#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} LOAD = FLASHD,
                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)
   #endif
#endif
						 
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1        PAGE = 1
   .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
   .esysmem            : > RAMLS5       PAGE = 1

   /* Initalized sections go in Flash */
   .econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
   
   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
   
   SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   
   /* The following section definitions are required when using the IPC API Drivers */ 
    GROUP : > CPU1TOCPU2RAM, PAGE = 1 
    {
        PUTBUFFER 
        PUTWRITEIDX 
        GETREADIDX 
    }
    
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }  
    
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

  • 0
    TI__Guru**** 251220 points

    Please see this forum thread.  While the original question is not identical, it is close.  The answer is the same for your problem.

    Thanks and regards,

    -George

  • 0 in reply to George Mock
    Expert 1050 points

    Hello Geroge,

    ok, i have read the thread you have linked.
    In a fast-try i tried my approach.

    I uncommented the predefined RAMGS2 area and defined two of my own, both of the size of 0x32 which is the space of 50 int16 types.
    I defined

    RAM_TEST_1 : origin = 0xE000, length = 0x32
    RAM_TEST_2 : origin = 0xE040, length = 0x32

    and in the SECTION area

    area1 .: > RAM_TEST_1, PAGE = 1
    area2 .: > RAM_TEST_2, PAGE = 1

    and in the c++ file i did

    #pragma DATASECTION("area1");
    int16 myArr1[50];

    #pragma DATASECTION("area2");
    int16 myArr2[50];

    Looking at the .map files this works. On both CPU´s the arrays are mapped to the same location.
    Is this a leagal way to go, or can it come to crashes during runtime for reasons i havn´t considered?

    Also, i noticed, that i needed to define the origin for RAM_TEST_2 to 0xE040, not 0xE032.
    Since 0x40 is dec.64 this doesn´t seem to be a cooincidence?

  • 0 in reply to user4221161
    TI__Guru**** 251220 points

    Unfortunately, you misunderstand the suggestion I made in the older forum thread.  The only way to control the order of data variables in memory is to define them not in C or C++, but in hand-coded assembly.  The details on doing that are given in that post. 

    The technique you show is one way to put a specific variable at a specific address.  But it is cumbersome, and prone to error.  Imagine doing that for around 25 different variables.

    Thanks and regards,

    -George