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Section filing algorithm?

Dave Smith62
Intellectual 405 points

Tool/software: TI C/C++ Compiler

Hi,

Need a clarification on linker placement order:

There is a bewildering array of directives, UNION, SPLIT, GROUP, MEMORY, SECTION, etc.

In case we already have an linked and fully relocated .out file, in which funA@addrA, funcB@addrB, … funcY@addrY, and they are in an object file Old.obj .

Then we compile a new funZ(), which references some of the previous functions, providing the necessary declarations, and compile to an un-relocated Z.obj file.

Then we added Z.obj to the previous project, link it with existing Old.obj (not PARTIAL linking, because we are NOT relinking with an .out file containing relocation information). So the only difference is we add Z.obj, which only has outward references that needs to be relocated.

Then, would any of {addrA, … addrY} change?

 

Not sure of this because we have no linker source, and there are suspicions:

  1. In http://processors.wiki.ti.com/index.php/Program_Cache_Layout#--preferred_order_Option, there is “a weighted call graph (WCG)” concept for v7 of C6000 which create preferred placement order when involving cache, etc.
  2. In old version of linkers there have always been "--preferred_order" option.

We exclude the use of either (new funZ() never alter any call count, etc.), in this simple situation, please

  1. Accurately describe how functions and symbols are allocated, when SECTION/MEMORY are all specified. Say we have section beginning at 0Xc0000000 for .text, which functions from which objs will be allocated first?
  2. Does this differ between DSPs and other processors? The DSP compiler writers might have more considerations like memory hierarchies vs performance in their mind, so has allocation algorithms been changed anyhow?
  3. The linking and symbol RESOLUTION is recursively, which is obvious. Is the placement just plain old linear placement, from say 0Xc0000000, one after another and never winding back?

 

Dave

  • 0
    Intellectual 405 points
    Taking into account near/far call, trampoline optimization and related issues, very probably that the placement algorithm is more involved? Perhaps I should not be on a plain-linear-imple assumption?
  • 0
    TI__Guru* 84285 points

    Indeed, the algorithm is quite involved.  Besides the issues you've noted, the linker also takes into consideration alignment, blocking, output section splitting, different load and run address, phase ordering, etc.  However, most of the time the linker's placement choices can be explained with these basic rules:

    1. Sections with exact placement are placed first because they can't go anywhere else
    2. Sections in a GROUP are placed together
    3. Larger sections are placed first, typically at the lowest address of the first memory remaining into which they fit
    4. If there are gaps between larger sections due to alignment, smaller sections may be squeezed between them

    The DSP compilers and MCU compilers use pretty much the same placement algorithm.  What may differ is the linker command file, which is specific to the device.  The linker command file can dramatically affect the placement.