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CCS: XDS100v2 USB Debug Probe and AM3352 Communication Problem

Evgeny Vainshtok33
Prodigy 150 points

Tool/software: Code Composer Studio

Hello, to all members.

Our board is very similar on Black Beagle Bone design and I am trying to port it with the JTAG.

I use XSD100v2 emulator and the instructions I followed are from Linux Board Porting Training Series.

I use the CCS v.7.3, the XDS100v2 by Blackhawlk

Test Connection result is - 

[Start: Texas Instruments XDS100v2 USB Debug Probe_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

/home/evgenyv/.ti/ti/0/0/BrdDat/testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'libjioserdesusb.so'.
The library build date was 'Jul 21 2017'.
The library build time was '19:29:13'.
The library package version is '7.0.48.0'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End: Texas Instruments XDS100v2 USB Debug Probe_0]

After attempt to Connect to target, there is this error pop up 

Error connecting to the target:
(Error -1170 @ 0x0)
Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK).
(Emulation package 7.0.48.0)

SYS_BOOT_5 is pulled up.

When I configured 100KHz on JTAG TCLK Frequency and got this on the logic analyzer:

When I configured the clock to 10.368 MHz I got the next error message:

Error connecting to the target:

(Error -1170 @ 0x0)
Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK).
(Emulation package 7.0.48.0)

 

Is it configuration?

Are these connections?

Is it license?

Is it debugger?

 

I am a new in the fielsdof Linux embedded development and new to the TI world, so I am sorry in advance if the questions are formulated unprofessionally.

 

  • 0
    TI__Guru**** 171034 points
    Hi,

    Error -1170 is described at:
    software-dl.ti.com/.../ccsv7_debugging_jtag_connectivity_issues.html

    Therefore, as it indicates, there is no issue in the connection between the Debug Probe and the device - thus the Test Connection does not show any errors (as you can also attest with the signaling captured by your Logic Analyzer).

    The problem is located inside the device and may be related either to faulty power or reset lines, bootmodes that prevent access to the cores or even pre-existing code that may be preventing the JTAG from gaining access to the core or powering down the Debug Subsystem.

    In order to validate the connections I would first try to see if the DAP can be accessed - check the short clip below:
    https://youtu.be/-yGmq_VKvTQ

    If the DAP cannot be accessed, there is a chance the device is either not powered properly or code running on the board is powering down the Debug Subsystem. You can first check the status of the cores as shown at the reference below:
    processors.wiki.ti.com/.../GSG:Connecting_to_slave_cores_in_SoC_devices_v5

    At last, check the post below with some tips to debug systems where Linux is running.

    e2e.ti.com/.../1994287

    Hope this helps,
    Rafael
  • 0 in reply to desouza
    Prodigy 150 points

    Hi, Rafael.

    I followed all the steps and tutorials. Seems like we did everything as needed.

    I will try to describe the process in more details

    1. Target Connect

    2. Signals are captured

    3. At this point, the CCS is stuck and only reconnecting the USB cable from the emulator releasing it.

    Sometimes the error is:

    (Error -1170 @ 0x0)
    Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK).
    (Emulation package 7.0.48.0)

    Sometimes:

    Error connecting to the target:
    (Error -1045 @ 0xFFFFFF66)
    The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation.
    (Emulation package 7.0.48.0)

     

    I was thinking to use another debugger, but I think the problem is not there.

  • 0 in reply to Evgeny Vainshtok33
    TI__Guru**** 171034 points
    Hi,

    >> 3. At this point, the CCS is stuck and only reconnecting the USB cable from the emulator releasing it.

    So, by "stuck" you mean that CCS screen freezes or it immediately throws the error you mentioned?

    If it freezes, I would try the steps shown at sections 4 and 6 of the Troubleshooting CCSv7 page at:
    processors.wiki.ti.com/.../Troubleshooting_CCSv7

    In addition to that, I would try to reduce the physical connections between the Debug Probe and the device to a minimum and see if the "freeze" goes away - sometimes the communications suffer severe lags due to retries.

    If the error message is shown after you unplug the cable, that would be expected as CCS lost communications with the target.

    If those tips do not help you, I would either try to isolate the issue by changing host PCs or start to become suspicious of the Debug Probe or the board itself - does the communication work well when using a regular development kit?

    Hope this helps,
    Rafael
  • 0 in reply to desouza
    Prodigy 150 points
    I powered up the board without any firmware on it and the JTAG emulator has connected successfully.
    So the problem is not the connector, but probably some software configuration prevents JTAG to work.
    Can you reffer me to relevant tutorials where the releationship betewwn the U-BOOT and JTAG are described.
    Thank you very much for your assistance.
  • 0 in reply to Evgeny Vainshtok33
    TI__Guru**** 171034 points
    Hi,

    >> Can you reffer me to relevant tutorials where the releationship betewwn the U-BOOT and JTAG are described.
    I am not aware of any specific tutorials in this regard and my knowledge quickly fades as the intricacies of U-boot and Linux kernel vary quite fast over the different versions.

    In this case, I think you will have better insights if you ask this question on the Sitara forum, as the experts there are much more up-to-date with the latest releases of embedded Linux.

    Regards,
    Rafael