Compiler/TMS320F28335: TMS320F28335

/* ==============================================================================
         Header files
=================================================================================*/
#include <stdlib.h>
#include "IQmathLib.h"         /* Include header for IQmath library */
//#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
//#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
//#include "DSP2833x_Examples.h"
#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h"
//#include "pmci.h"
//#include "parameter.h"
//#include "build.h"
//#include "DSP2833x_GlobalPrototypes.h" //for setting up SCI, SPI and XF

void mailbox_check(int32 T1, int32 T2, int32 T3);
void mailbox_read(int16 i);

float32 AngleOffset = 10.123;
Uint16 MaxRMSPhaseCurrent = 200;
Uint16 MaxIqCommand = 10;
float32 MaxPhaseCurrent = 300.123;

float32 TorqueCommand = 123.456;
Uint16 EnableCommand =1;
Uint16 DirectionBit= 0;

Uint16 IdKi =50;
Uint16 IdKp = 100;
Uint16 IqKi =50;
Uint16 IqKp =100;

Uint16 MinBattCurrentForRegenBraking = 123;
Uint16 HysteresisRegenBraking = 50;

Uint16 RollingCounter = 123;
Uint16 MaxRollingCounterErrors = 5;

float32 IaRMS =100.123;
float32 IbRMS =100.123;
float32 IcRMS =100.123;
float32 DCLinkVoltage =650.111;

Uint16 RawPosition = 12;
Uint16 Position = 12;
float32 Thetam = 0.123456;
float32 VelocityRPM = 321.123;

float32 IqTableCommand = 123.456;
float32 IdTableCommand = 123.456;
float32 IqFeedback = 123.456;
float32 IdFeedback = 123.456;

Uint32 FaultRegA  = 0;
Uint16 EventManager1 = ((Data2) & 0x0000FFFF));
Uint16 EventManager2 = ((Data2) & 0xFFFF0000)>>16);

Uint16 ResolverConfigured =1;;
Uint16 Enabled            =1;
Uint16 Fault              = 0;

float32 DCLinkCurrent       = 123.456;
Uint16 InverterTemperature = 25;
Uint16 MotorTemperature    = 35;

Uint32 HVB_BatteryCurrent       = 123456789;
Uint16 HVB_ContactorClosed      = 0;
Uint16 HVB_ContactorOpenRequest = 0;
Uint16 HVB_Fault                = 0;


// Global variable for this example
Uint32  ErrorCount;
Uint32  MessageReceivedCount;

Uint32  TestMbox1 = 0;
Uint32  TestMbox2 = 0;
Uint32  TestMbox3 = 0;


/*int main(void)
{
    //InitECana();
    hwi_can_init();
   // CANtransmit();
    //CAN_Receive();
	return 0;
}
*/


void main(void)
{

    Uint16  i,j;

// eCAN control registers require read/write access using 32-bits.  Thus we
// will create a set of shadow registers for this example.  These shadow
// registers will be used to make sure the access is 32-bits and not 16.
   struct ECAN_REGS ECanaShadow;

// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP281x_SysCtrl.c file.
   InitSysCtrl();

// Step 2. Initalize GPIO:
// This example function is found in the DSP281x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
 //InitGpio();  // Skipped for this example

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
   DINT;

// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP281x_PieCtrl.c file.
//   InitPieCtrl(); // Skipped for this example

// Disable CPU interrupts and clear all CPU interrupt flags:
   IER = 0x0000;
   IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in DSP281x_DefaultIsr.c.
// This function is found in DSP281x_PieVect.c.
//   InitPieVectTable();    // Skipped for this example

// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP281x_InitPeripherals.c
// InitPeripherals(); // Not required for this example

// Step 5. User specific code

    MessageReceivedCount = 0;
    ErrorCount = 0;

    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.ECANAENCLK= 1;  //    Enable system clk to eCAN-A

    GpioCtrlRegs.GPAPUD.all = 0x0000;      // Pullup's enabled GPIO0-GPIO31



    InitECan();     // Initialize the eCAN module
/*
    // Mailboxs can be written to 16-bits or 32-bits at a time
    // Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 15
    ECanaMboxes.MBOX0.MSGID.all = 0x9555AAA0;
    ECanaMboxes.MBOX1.MSGID.all = 0x9555AAA1;
    ECanaMboxes.MBOX2.MSGID.all = 0x9555AAA2;
    ECanaMboxes.MBOX3.MSGID.all = 0x9555AAA3;
    ECanaMboxes.MBOX4.MSGID.all = 0x9555AAA4;
    ECanaMboxes.MBOX5.MSGID.all = 0x9555AAA5;
    ECanaMboxes.MBOX6.MSGID.all = 0x9555AAA6;
    ECanaMboxes.MBOX7.MSGID.all = 0x9555AAA7;
    ECanaMboxes.MBOX8.MSGID.all = 0x9555AAA8;
    ECanaMboxes.MBOX9.MSGID.all = 0x9555AAA9;
    ECanaMboxes.MBOX10.MSGID.all = 0x9555AAAA;
    ECanaMboxes.MBOX11.MSGID.all = 0x9555AAAB;
    ECanaMboxes.MBOX12.MSGID.all = 0x9555AAAC;
    ECanaMboxes.MBOX13.MSGID.all = 0x9555AAAD;
    ECanaMboxes.MBOX14.MSGID.all = 0x9555AAAE;
    ECanaMboxes.MBOX15.MSGID.all = 0x9555AAAF;
*/
        ECanaMboxes.MBOX0.MSGID.all = 0x201;
        ECanaMboxes.MBOX1.MSGID.all = 0x202;
        ECanaMboxes.MBOX2.MSGID.all = 0x203;
        ECanaMboxes.MBOX3.MSGID.all = 0x204;
        ECanaMboxes.MBOX4.MSGID.all = 0x205;
        ECanaMboxes.MBOX5.MSGID.all = 0x101;
        ECanaMboxes.MBOX6.MSGID.all = 0x102;
        ECanaMboxes.MBOX7.MSGID.all = 0x103;
        ECanaMboxes.MBOX8.MSGID.all = 0x104;
        ECanaMboxes.MBOX9.MSGID.all = 0x105;
        ECanaMboxes.MBOX10.MSGID.all = 0x106;
        ECanaMboxes.MBOX11.MSGID.all = 0x107;

        ECanaMboxes.MBOX12.MSGID.all = 0x9555AAAC;
        ECanaMboxes.MBOX13.MSGID.all = 0x9555AAAD;
        ECanaMboxes.MBOX14.MSGID.all = 0x9555AAAE;
        ECanaMboxes.MBOX15.MSGID.all = 0x9555AAAF;

    // Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31
    ECanaMboxes.MBOX16.MSGID.all = 0x9555BBB0;
    ECanaMboxes.MBOX17.MSGID.all = 0x9555BBB1;
    ECanaMboxes.MBOX18.MSGID.all = 0x9555BBB2;
    ECanaMboxes.MBOX19.MSGID.all = 0x9555BBB3;
    ECanaMboxes.MBOX20.MSGID.all = 0x9555BBB4;
    ECanaMboxes.MBOX21.MSGID.all = 0x9555AAA5;
    ECanaMboxes.MBOX22.MSGID.all = 0x9555AAA6;
    ECanaMboxes.MBOX23.MSGID.all = 0x9555AAA7;
    ECanaMboxes.MBOX24.MSGID.all = 0x9555AAA8;
    ECanaMboxes.MBOX25.MSGID.all = 0x9555AAA9;
    ECanaMboxes.MBOX26.MSGID.all = 0x9555AAAA;
    ECanaMboxes.MBOX27.MSGID.all = 0x9555AAAB;
    ECanaMboxes.MBOX28.MSGID.all = 0x9555AAAC;
    ECanaMboxes.MBOX29.MSGID.all = 0x9555AAAD;
    ECanaMboxes.MBOX30.MSGID.all = 0x9555AAAE;
    ECanaMboxes.MBOX31.MSGID.all = 0x9555AAAF;

    // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANMD.all = 0xFFFF0000;

    // Enable all Mailboxes */
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    //ECanaRegs.CANME.all = 0xFFFFFFFF; //Commented 02-02-2018
    ECanaRegs.CANME.all = 0x00010001;  //Enable 02-02-2018

    // Specify that 8 bits will be sent
  /*
    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8;
*/
    // Added here 02-02-2018
        ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
        ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 3;
        ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
        ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 2;
        ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 2;
        ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
        ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
        ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
        ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
        ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 1;
        ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 4;
        ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 5;

        ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8;
        ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8;
        ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8;
        ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8;

    // Write to the mailbox RAM field of MBOX0 - 15
    //ECanaMboxes.MBOX0.MDL.all = 0x9555AAA0;
    //ECanaMboxes.MBOX0.MDH.all = 0x89ABCDEF;

  /*
    ECanaMboxes.MBOX0.MDL.all = 0x11223344;
    ECanaMboxes.MBOX0.MDH.all = 0x55667788;

    ECanaMboxes.MBOX1.MDL.all = 0x9555AAA1;
    ECanaMboxes.MBOX1.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX2.MDL.all = 0x9555AAA2;
    ECanaMboxes.MBOX2.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX3.MDL.all = 0x9555AAA3;
    ECanaMboxes.MBOX3.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX4.MDL.all = 0x9555AAA4;
    ECanaMboxes.MBOX4.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX5.MDL.all = 0x9555AAA5;
    ECanaMboxes.MBOX5.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX6.MDL.all = 0x9555AAA6;
    ECanaMboxes.MBOX6.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX7.MDL.all = 0x9555AAA7;
    ECanaMboxes.MBOX7.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX8.MDL.all = 0x9555AAA8;
    ECanaMboxes.MBOX8.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX9.MDL.all = 0x9555AAA9;
    ECanaMboxes.MBOX9.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX10.MDL.all = 0x9555AAAA;
    ECanaMboxes.MBOX10.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX11.MDL.all = 0x9555AAAB;
    ECanaMboxes.MBOX11.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX12.MDL.all = 0x9555AAAC;
    ECanaMboxes.MBOX12.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX13.MDL.all = 0x9555AAAD;
    ECanaMboxes.MBOX13.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX14.MDL.all = 0x9555AAAE;
    ECanaMboxes.MBOX14.MDH.all = 0x89ABCDEF;

    ECanaMboxes.MBOX15.MDL.all = 0x9555AAAF;
    ECanaMboxes.MBOX15.MDH.all = 0x89ABCDEF;
    */
// Added from here 02-02-2018

            ECanaMboxes.MBOX0.MDL.byte.BYTE0 = ((Uint16)(AngleOffset*100) & 0x00FF);
            ECanaMboxes.MBOX0.MDL.byte.BYTE1 = ((Uint16)(AngleOffset*100) & 0xFF00)>>8);
            ECanaMboxes.MBOX0.MDL.byte.BYTE2 = ((Uint16)(MaxRMSPhaseCurrent) & 0x00FF);
            ECanaMboxes.MBOX0.MDL.byte.BYTE3 = ((Uint16)(MaxRMSPhaseCurrent) & 0xFF00)>>8);
            ECanaMboxes.MBOX0.MDH.byte.BYTE4 = ((Uint16)(MaxIqCommand) & 0x00FF);
            ECanaMboxes.MBOX0.MDH.byte.BYTE5 = ((Uint16)(MaxIqCommand) & 0xFF00)>>8);
            ECanaMboxes.MBOX0.MDH.byte.BYTE6 = ((Uint16)(MaxPhaseCurrent*100) & 0x00FF);
            ECanaMboxes.MBOX0.MDH.byte.BYTE7 = ((Uint16)(MaxPhaseCurrent*100) & 0xFF00)>>8);

            //Tx Message2 Packing
            ECanaMboxes.MBOX1.MDL.byte.BYTE0 = ((Uint16)(TorqueCommand*100) & 0x00FF);
            ECanaMboxes.MBOX1.MDL.byte.BYTE1 = ((Uint16)(TorqueCommand*100) & 0xFF00)>>8);
            ECanaMboxes.MBOX1.MDL.byte.BYTE2 = (EnableCommand & 0x0001) | ((DirectionBit & 0x0001)<<1)  ;


            //Tx Message3
            ECanaMboxes.MBOX2.MDL.byte.BYTE0 = (IdKi & 0x00FF);
            ECanaMboxes.MBOX2.MDL.byte.BYTE1 = (IdKi & 0xFF00)>>8);
            ECanaMboxes.MBOX2.MDL.byte.BYTE2 = (IdKp & 0x00FF);
            ECanaMboxes.MBOX2.MDL.byte.BYTE3 = (IdKp & 0xFF00)>>8);
            ECanaMboxes.MBOX2.MDH.byte.BYTE4 = (IqKi & 0x00FF);
            ECanaMboxes.MBOX2.MDH.byte.BYTE5 = (IqKi & 0xFF00)>>8);
            ECanaMboxes.MBOX2.MDH.byte.BYTE6 = (IqKp & 0x00FF);
            ECanaMboxes.MBOX2.MDH.byte.BYTE7 = (IqKp & 0xFF00)>>8);

            //Tx Message4
            ECanaMboxes.MBOX3.MDL.byte.BYTE0 = ((Uint16)(MinBattCurrentForRegenBraking) & 0x00FF>>8);
            ECanaMboxes.MBOX3.MDL.byte.BYTE1 = ((Uint16)(HysteresisRegenBraking) & 0x00FF >>8);

            //Tx Message5
            ECanaMboxes.MBOX4.MDL.byte.BYTE0 = ((Uint16)(RollingCounter) & 0x00FF>>8);
            ECanaMboxes.MBOX4.MDL.byte.BYTE1 = ((Uint16)(MaxRollingCounterErrors) & 0x00FF>>8);

            //Control Feedback1
            ECanaMboxes.MBOX5.MDL.byte.BYTE0 = ((Uint16)(IaRMS*125) & 0x00FF);
            ECanaMboxes.MBOX5.MDL.byte.BYTE1 = ((Uint16)(IaRMS*125) & 0xFF00)>>8);
            ECanaMboxes.MBOX5.MDL.byte.BYTE2 = ((Uint16)(IbRMS*125) & 0x00FF);
            ECanaMboxes.MBOX5.MDL.byte.BYTE3 = ((Uint16)(IbRMS*125) & 0xFF00)>>8);
            ECanaMboxes.MBOX5.MDH.byte.BYTE4 = ((Uint16)(IcRMS*125) & 0x00FF);
            ECanaMboxes.MBOX5.MDH.byte.BYTE5 = ((Uint16)(IcRMS*125) & 0xFF00)>>8);
            ECanaMboxes.MBOX5.MDH.byte.BYTE6 = ((Uint16)(DCLinkVoltage*50) & 0x00FF);
            ECanaMboxes.MBOX5.MDH.byte.BYTE7 = ((Uint16)(DCLinkVoltage*50) & 0xFF00)>>8);

            //Control Feedback2 Packing
            ECanaMboxes.MBOX6.MDL.byte.BYTE0 = ((Uint16)RawPosition & 0x00FF);
            ECanaMboxes.MBOX6.MDL.byte.BYTE1 = ((Uint16)RawPosition & 0xFF00)>>8);
            ECanaMboxes.MBOX6.MDL.byte.BYTE2 = ((Uint16)Position & 0x00FF);
            ECanaMboxes.MBOX6.MDL.byte.BYTE3 = ((Uint16)Position & 0xFF00)>>8);
            ECanaMboxes.MBOX6.MDH.byte.BYTE4 = ((Uint16)(Thetam*5000) & 0x00FF);
            ECanaMboxes.MBOX6.MDH.byte.BYTE5 = ((Uint16)(Thetam*5000) & 0xFF00)>>8);
            ECanaMboxes.MBOX6.MDH.byte.BYTE6 = ((Uint16)(VelocityRPM*2.5) & 0x00FF);
            ECanaMboxes.MBOX6.MDH.byte.BYTE7 = ((Uint16)(VelocityRPM*2.5) & 0xFF00)>>8);

            //Control Feedback3 Packing
            ECanaMboxes.MBOX7.MDL.byte.BYTE0 = ((Uint16)(IqTableCommand*33.34) & 0x00FF);
            ECanaMboxes.MBOX7.MDL.byte.BYTE1 = ((Uint16)(IqTableCommand*33.34) & 0xFF00)>>8);
            ECanaMboxes.MBOX7.MDL.byte.BYTE2 = ((Uint16)(IdTableCommand*33.34) & 0x00FF);
            ECanaMboxes.MBOX7.MDL.byte.BYTE3 = ((Uint16)(IdTableCommand*33.34) & 0xFF00)>>8);
            ECanaMboxes.MBOX7.MDH.byte.BYTE4 = ((Uint16)(IqFeedback*33.34) & 0x00FF);
            ECanaMboxes.MBOX7.MDH.byte.BYTE5 = ((Uint16)(IqFeedback*33.34) & 0xFF00)>>8);
            ECanaMboxes.MBOX7.MDH.byte.BYTE6 = ((Uint16)(IdFeedback*33.34) & 0x00FF);
            ECanaMboxes.MBOX7.MDH.byte.BYTE7 = ((Uint16)(IdFeedback*33.34) & 0xFF00)>>8);

            //Control Feedback4 Packing
            ECanaMboxes.MBOX8.MDL.byte.BYTE0 = ((Uint32)IqTableCommand & 0x000000FF);
            ECanaMboxes.MBOX8.MDL.byte.BYTE1 = (((Uint32)IqTableCommand & 0x0000FF00)>>8);
            ECanaMboxes.MBOX8.MDL.byte.BYTE2 = (((Uint32)IqTableCommand & 0x00FF0000)>>16);
            ECanaMboxes.MBOX8.MDL.byte.BYTE3 = (((Uint32)IqTableCommand & 0xFF000000)>>24);
            ECanaMboxes.MBOX8.MDH.byte.BYTE4 = ((Uint16)EventManager1 & 0x00FF);
            ECanaMboxes.MBOX8.MDH.byte.BYTE5 = ((Uint16)EventManager1 & 0xFF00)>>8);
            ECanaMboxes.MBOX8.MDH.byte.BYTE6 = ((Uint16)EventManager2 & 0x00FF);
            ECanaMboxes.MBOX8.MDH.byte.BYTE7 = ((Uint16)EventManager2 & 0xFF00)>>8);

            //Control Feedback5 Packing
            ECanaMboxes.MBOX9.MDL.byte.BYTE0 = ((Uint16)ResolverConfigured & 0x0001|(((Uint16)Enabled & 0x0001) <<1) | (((Uint16)Fault & 0x0001)<<2));

            //Control Feedback6 Packing
            ECanaMboxes.MBOX10.MDL.byte.BYTE0 = ((Uint16)(DCLinkCurrent*50) & 0x00FF);
            ECanaMboxes.MBOX10.MDL.byte.BYTE1 = ((Uint16)(DCLinkCurrent*50) & 0xFF00)>>8);
            ECanaMboxes.MBOX10.MDL.byte.BYTE2 = (((Uint16)InverterTemperature)>>8);
            ECanaMboxes.MBOX10.MDL.byte.BYTE3 = (((Uint16)MotorTemperature)>>8);

            //HVB Data Packing
            ECanaMboxes.MBOX11.MDL.byte.BYTE0 = ((Uint32)HVB_BatteryCurrent & 0x000000FF);
            ECanaMboxes.MBOX11.MDL.byte.BYTE1 = (((Uint32)HVB_BatteryCurrent & 0x0000FF00)>>8);
            ECanaMboxes.MBOX11.MDL.byte.BYTE2 = (((Uint32)HVB_BatteryCurrent & 0x00FF0000)>>16);
            ECanaMboxes.MBOX11.MDL.byte.BYTE3 = (((Uint32)HVB_BatteryCurrent & 0xFF000000)>>24);
            ECanaMboxes.MBOX11.MDH.byte.BYTE4 = (((Uint16)HVB_ContactorClosed & 0x0001) | (((Uint16)HVB_ContactorOpenRequest & 0x0001)<<2) | (((Uint16)HVB_Fault & 0x0001)<<3));






    // Configure the eCAN for self test mode
    // Enable the enhanced features of the eCAN.

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.STM = 1;    // Configure CAN for self-test mode
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;


    /* Configure bit timing parameters for eCANA  BaudRates */
        ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
        ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
        ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

        ECanaShadow.CANES.all = ECanaRegs.CANES.all;

        do
        {
            ECanaShadow.CANES.all = ECanaRegs.CANES.all;
        } while(ECanaShadow.CANES.bit.CCE != 1 );       // Wait for CCE bit to be set..

        ECanaShadow.CANBTC.all = 0;

        #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
            /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
               See Note at End of File */
                ECanaShadow.CANBTC.bit.BRPREG = 9; // 4 for 1Mbps, 9 for 500Kbps, 19 for 250Kbps, 39 for 125Kbps, 49 for 100Kbps
                ECanaShadow.CANBTC.bit.TSEG2REG = 2;
                ECanaShadow.CANBTC.bit.TSEG1REG = 10;
        #endif
        #if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
        /* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
           See Note at End of File */
            ECanaShadow.CANBTC.bit.BRPREG = 4; // 4 for 1Mbps, 9 for 500Kbps, 19 for 250Kbps, 39 for 125Kbps, 49 for 100Kbps
            ECanaShadow.CANBTC.bit.TSEG2REG = 1;
            ECanaShadow.CANBTC.bit.TSEG1REG = 6;
        #endif


        ECanaShadow.CANBTC.bit.SAM = 1;
        ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

        ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
        ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
        ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

        ECanaShadow.CANES.all = ECanaRegs.CANES.all;

        do
        {
           ECanaShadow.CANES.all = ECanaRegs.CANES.all;
        } while(ECanaShadow.CANES.bit.CCE != 0 );       // Wait for CCE bit to be  cleared..



//*********************************************************************
    if (1){ // for the CAN A

        //GpioCtrlRegs.GPADIR.bit.GPIO30  = 0;  //0=input,  1=output
        //GpioCtrlRegs.GPADIR.bit.GPIO31  = 1;  //0=input,  1=output
        //GpioCtrlRegs.GPAQSEL2.all = 0x0000;    // GPIO16-GPIO31 Synch to SYSCLKOUT
        //GpioCtrlRegs.GPAQSEL1.all = 0x05000000L;    // No qualification for all group A GPIO 0-15
        //GpioCtrlRegs.GPAQSEL2.all = 0x00000000L;    // No qualification for all group A GPIO 16-31
        GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;   // Enable pullup on GPIO30
        GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;   // Enable pullup on GPIO31
        GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 3; // Asynch input
        GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; //GPIO30: 0=GPIO, 1=CANRXA    2=rsvd       3=rsvd
        GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; //GPIO31: 0=GPIO, 1=CANTXA    2=rsvd       3=rsvd
       // GpioCtrlRegs.GPACTRL.all  = 0x00003200L;    // QUALPRD = SYSCLKOUT for all group A GPIO

    }
    else{ // For the General Pupose IO
        GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0; //GPIO30: 0=GPIO, 1=CANRXA    2=rsvd       3=rsvd
        GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0; //GPIO31: 0=GPIO, 1=CANTXA    2=rsvd       3=rsvd
        GpioCtrlRegs.GPADIR.bit.GPIO30  = 0;  //0=input,  1=output
        GpioCtrlRegs.GPADIR.bit.GPIO31  = 0;  //0=input,  1=output
        GpioCtrlRegs.GPAQSEL2.all = 0x0000;    // GPIO16-GPIO31 Synch to SYSCLKOUT

    };

    //GpioDataRegs.GPADAT.bit.GPIO31 = 1;
    //GpioDataRegs.GPASET.bit.GPIO31 =1;
   // for (i=0;i<1000;i++){}//delay
   // GpioDataRegs.GPADAT.bit.GPIO31 = 0;
    //GpioDataRegs.GPACLEAR.bit.GPIO30 = 1;

//*******************************************************************8
    EDIS;

    // Begin transmitting
    while(1)
    {
//**************
      //  GpioDataRegs.GPADAT.bit.GPIO31 = 1;
        //GpioDataRegs.GPASET.bit.GPIO31 =1;
       // for (i=0;i<1000;i++){}//delay
       // GpioDataRegs.GPADAT.bit.GPIO31 = 0;
        //GpioDataRegs.GPACLEAR.bit.GPIO30 = 1;
//****************

       ECanaRegs.CANTRS.all = 0x0000FFFF;  // Set TRS for all transmit mailboxes
       while(ECanaRegs.CANTA.all != 0x0000FFFF ) {}  // Wait for all TAn bits to be set..
       ECanaRegs.CANTA.all = 0x0000FFFF;   // Clear all TAn
       MessageReceivedCount++;

       //Read from Receive mailboxes and begin checking for data */
       for(j=16; j<31; j++)         // Read & check 16 mailboxes
       {
          mailbox_read(j);         // This func reads the indicated mailbox data
          mailbox_check(TestMbox1,TestMbox2,TestMbox3); // Checks the received data
       }
    }
}

// This function reads out the contents of the indicated
// by the Mailbox number (MBXnbr).
void mailbox_read(int16 MBXnbr)
{
   volatile struct MBOX *Mailbox;
   Mailbox = &ECanaMboxes.MBOX0 + MBXnbr;
   TestMbox1 = Mailbox->MDL.all; // = 0x9555AAAn (n is the MBX number)
   TestMbox2 = Mailbox->MDH.all; // = 0x89ABCDEF (a constant)
   TestMbox3 = Mailbox->MSGID.all;// = 0x9555BBBn (n is the MBX number)

} // MSGID of a rcv MBX is transmitted as the MDL data.


void mailbox_check(int32 T1, int32 T2, int32 T3)
{
    if((T1 != T3) || ( T2 != 0x89ABCDEF))
    {
       ErrorCount++;
    }
}


//===========================================================================
// No more.
//===========================================================================

/* Note:
As indicated in the 281x device errata (SPRZ193), double-reads/double writes should be
employed for accesses to the mailbox RAM & LAM/MOTO/MOTS areas. Note, however, that the
errata is applicable only if the mailbox RAM & LAM/MOTO/MOTS areas are accessed at the
same time. The header file example operates in self-test mode, with no possibility of
a contention. Hence, the workaround is not implemented. When eCAN is communicating with
another node in non self-test mode), the workaround must be incorporated.
*/