CCS/AM5728: Miscellaneous issues with debugging with Blackhawk XDS 560v2

Hi,

1) Unfortunately ETB is quite small and is exhausted quite quickly on a 1GHz part. Certain architectures allow halting the core when ETB is filled, but I don't think this is supported on Cortex A, but I couldn't find any reference that confirms that. I will have to double check this.

2) The Debugger GUI does not have knowledge about the clock speed of the device and ETB does not carry timestamp information, therefore this message is displayed. ProTrace allows gathering more precise timestamps due to the additional bandwidth.
The lack of data is most probably due to the fact you are either running your code entirely from the internal RAM or there is no data transfers between the internal RAM or a peripheral (DMA, for example) and the EMIF. The measurable throughput is then zero.

3) A similar scenario as before. If cache is not enabled, the cache events are not existent. However, in your particular case the core is still running and you should see data when it is stopped.

4) The warning message is a similar scenario as 1) above. The lack of any graph drawing is due to 3) above (core not halted)

Hope this helps,
Rafael

Thank you very much Rafael.

3) A similar scenario as before. If cache is not enabled, the cache events are not existent. However, in your particular case the core is still running and you should see data when it is stopped.

True. In my case since the core is running, I should see some data when it is halted. But I am unable to see that. What else could be an issue. Do you want me to check something and report back? OR if you need more information then I can make a video and attach it here too.

One more question. Regarding setting operating points for doing power management, something like below, is it possible with using Linux processor SDK (i mean without using RTOS SDK)?

http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_PM

Hi,

Is your cache enabled? If so, make sure it is associated with the external memory region you are trying to access (I don't know the device that well to check how this is properly configured). For the data throughput trace, I usually define an external memory region and initiate a transfer from internal to external memory - an example of how to do this is attached - feel free to adapt to your own target. 

Regarding the power management details. Looking at the wiki page you mentioned, I suspect there is either a Linux application that sets these parameters or even some Kernel settings.However, I am not familiar enough with the device and its Linux implementation - in this case, I will ask someone from the Sitara group to give you a more knowledgeable reply.

Regards,

Rafael

MEM_Throughput_Multicore_A15.rar

Please refer to the below guide as it should address your Linux PM questions:

http://processors.wiki.ti.com/index.php/Linux_Core_Power_Management_User's_Guide_(v4.4)

@Rafael
>> Is your cache enabled? If so, make sure it is associated with the external memory region you are trying to access (I don't know the device that >> well to check how this is properly configured).

How do I check if the cache is enabled? I mean where do I enable it? In the .lds file?

Currently, the begining of the lds file looks something like below. It seems to define the external DDR memory and L3 cache. But, no L1 and L2. Am I right? Is this where, I need to modify it?

MEMORY
{

OCMC_RAM1 : o = 0x40300000, l = 0x00080000 /* 512kB L3 OCMC RAM1 */
OCMC_RAM2 : o = 0x40400000, l = 0x00100000 /* 1MB L3 OCMC RAM2 */
OCMC_RAM3 : o = 0x40500000, l = 0x00100000 /* 1MB L3 OCMC RAM3 */
DDR0 : o = 0x80000000, l = 0x40000000 /* 1GB external DDR Bank 0 */
DDR1 : o = 0xC0000000, l = 0x40000000 /* 1GB external DDR Bank 1 */

}

@RonB

I am looking for power management libraries to work with while doing bare metal programming (No Linux is running). That means, I would like to know and control the clock frequency/voltage my CPU is running my bare metal program.

desouza If you have time, could you please answer my question regarding enabling caches? Thank you so much.

solid repellent said:

How do I check if the cache is enabled?

The CCS Tools -> ARM Advanced Features view shows if the Data Cache and Instruction Cache are enabled. E.g. for a SYS/BIOS program for a Cortex-A15 core of an AM5728 which has enabled the cache:

solid repellent said:

I mean where do I enable it?

The I (Instruction cache enable) and C (Cache enable) bits in the Cortex-A15 SCTLR System Control Register are used to enable the caches. In order to get the performance improvement of data being placed in the cache requires the MMU to be enabled to define cacheable memory areas. If you are writing a bare metal program, PROCESSOR-SDK-RTOS-AM57X contains CSL functions for enabling the MMU and cache. See ti-processor-sdk-rtos-am57xx-evm-04.00.00.04\pdk_am57xx_1_0_7\packages\ti\csl\example\mmu\a15_data_validation\mmu_a15_data_validation_app_main.c for an example.

solid repellent said:

3) from PC trace > cache event profiler, I also see nothing. Is it supported for my debugger?

The Cache Event Profiler and Stall Cycle Profiler are only supported on C6000 DSP cores (see the Types of Traces and Their Uses section of Trace Analyzer User’s Guide).

With an AM5728 CCS 7.4 the Tools -> Hardware Trace Analyzer "Stall Profiling" and "Cache Analysis" options are greyed out for the Cortex-A15 cores and reported as "Not applicable on selected CPUs". However, CCS still allows the "Cache Event Profiler" and "Stall Cycle Profiler" analysis views to be opened from the "PC Trace" view on a Cortex-A15. Given that the Cache Event Profiler is not supported for a Cortex-A15, that explains why it shows nothing.