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CCS/TM4C1294NCPDT: Debug Error: No source available for "0xfffffff8"

Part Number: TM4C1294NCPDT
Other Parts Discussed in Thread: EK-TM4C1294XL

Tool/software: Code Composer Studio

SUMMARY: While debugging, when I return from an assembly function with the code bx lr (with lr holding 0xfffffff9), the session is interrupted and CCS returns an error saying: No source available for "0xfffffff8". It should start the return from ISR process (because of the 0xfffffff9 code) but looks like CCS Debugger can't handle this. So it tries to execute code from 0xfffffff8.

DETAILS:

I'm working on the thread management of a little operating system. To create threads I need to define their initial stack frame. The initial stack frame I'm creating is such that after a context switch a new thread will start executing as if it was returning from an ISR. Something like this:

#define PSR_RESET_VALUE   0x01000000
#define RFI_CODE          0xFFFFFFF9  // return from interrupt

/* -------------------------- */
/* CREATE INITIAL STACK FRAME */

*(--stack_pointer) = PSR_RESET_VALUE;       // PSR
*(--stack_pointer) = (uint32_t) routine;    // PC   (routine is the function executed by the thread)
*(--stack_pointer) = (uint32_t) destroy;    // LR   (destroy is the function that should be executed if routine returns)

// each GPR is initialized with its number just
// for debugging purposes
*(--stack_pointer) = 0x12121212;            // R12
*(--stack_pointer) = 0x03030303;            // R3
*(--stack_pointer) = 0x02020202;            // R2
*(--stack_pointer) = 0x01010101;            // R1
*(--stack_pointer) = 0x00000000;            // R0
*(--stack_pointer) = 0x11111111;            // R11
*(--stack_pointer) = 0x10101010;            // R10
*(--stack_pointer) = 0x09090909;            // R9
*(--stack_pointer) = 0x08080808;            // R8
*(--stack_pointer) = 0x07070707;            // R7
*(--stack_pointer) = 0x06060606;            // R6
*(--stack_pointer) = 0x05050505;            // R5
*(--stack_pointer) = 0x04040404;            // R4

// simulates a return from an ISR, so the registers
// are popped from the stack correctly
*(--stack_pointer) = RFI_CODE;

After the stack frame preparation is finished the stack pointer of the new thread will point to RFI_CODE (0xfffffff9). I will pop that code into LR before returning from context switch. So I was hoping the hardware would unstack everything correctly and the new thread would start executing. The code for context switch is here:

switch_context: 
    cpsid i         ; disable interrupts
    push {r4-r11}   ; push callee-save registers
    push {lr}	    ; lr is the address to return next time thread executes
    str  sp, [r0]   ; save hardware sp on current thread tcb.sp (r0 is the address of current thread tcb.sp)
    ldr  sp, [r1]   ; load hardware sp with new thread tcb.sp   (r1 is the address of new thread tcb.sp)
    pop  {lr}       ; pop address to return (in the first execution lr will be 0xfffffff9
    pop  {r4-r11}   ; pop callee-save registers
    cpsie i	    ; enable interrupts
    bx	 lr	    ; continue to execute from where thread was preempted before (in the first execution return from ISR)

The problem is already stated on the summary. When the processor returns from switch_context it should unstack the core registers's contents, as if it was returning from an ISR, and continues to execute. Instead, the debugging session is stopped and CCS says No source available for "0xfffffff8". I don't know why this is not working as I expected and I don't know why it goes to 0xfffffff8 instead of returning from ISR.

In this question a community member says this can be a debugger problem. Once there is no code at address 0xfffffff9, the debugger gets confused. If this is true, how can I continue debugging my code?

MORE INFO:

  • Windows 7 64-bit, Service Pack 1
  • CCS 7.4.0.00015 
  • LaunchPad EK-TM4C1294XL
  • Stellaris In-Circuit Debug Interface

  • I think I may have made a mistake. In my code I add 0xfffffff9 to the initial stack frame just to force the processor to unstack everything as if it was returning from an ISR even when the running thread make a system call to switch context outside an ISR. That way I could guarantee the initial stack frame would always be popped from the stack correctly. 

    But now I'm aware of the PendSV interrupt. This is the one I need to use to switch context, right?

    Sorry for the mistake.

    I suppose the error occurs because the processor needs to be in handler mode to be able to execute bx lr (0xfffffff9) correctly. But I still don't understand why it tries to continue execution from address 0xfffffff8 instead of 0xfffffff9.

  • Hi,

    I am not an expert in the Cortex M4 cores, therefore I will notify some device experts to look into your case.

    At any rate, the PendSV is the correct interrupt to perform RTOS context switch, according to ARM's CM4 TRM:
    infocenter.arm.com/.../index.jsp

    I found several discussions and resources on the internet covering the usage of PendSV and I highlight three of them below:
    https://youtu.be/tqRs5-Z8RRw
    community.arm.com/.../question-about-application-of-pendsv
    community.arm.com/.../how-to-invoke-arm-cortex-m3-pendsv-handle

    Regarding the debugger apparent inability to access the odd address, there may be a chance it is not expecting an unaligned access due to context or it may well be a bug.

    Therefore I ask: does the code execute normally even with the debugger warning? If so, the suspicion of a bug increases and it would be critical to have a small project that could reproduce the issue for analysis.

    On the other hand, if the code fails at this point, there is a possibility the unaligned code access is invalid from the core standpoint. I would then take a look at several discussions that mention unsupported access with unaligned code:
    community.arm.com/.../how-unaligned-address-is-handled-in-arm-cortex-m4
    stackoverflow.com/.../unaligned-access-causes-error-on-arm-cortex-m4

    Hope this helps,
    Rafael