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Veneer Code is not generated with #pragma DUAL, --abi=eabi and --code_state=16 for 4.6.4 TMS470 Compiler

Pashan
Intellectual 715 points

Hello,

I am using TMS470 Version 4.6.4.

In my souce code I have

#pragma DUAL_STATE(isr_SWI)
unsigned32_T isr_SWI(unsigned32_T param1, unsigned32_T param2, unsigned32_T dummy_reg)

with compiler options :

--abi=eabi and --code_state=16

In the ASSEMBLY Listing file I don't see the VENEER Code being generated for 32-Bit ARM as well as 16-Bit THUMB subroutine entry points.

Please help me soon with the reason for absence of VENEER Code.

Thank you.

Regards

Pashan

 

  • 0
    TI__Expert 4540 points

    Pashan,

    For EABI, veneer code is not generated by the compiler. It is instead generated by the linker, only if a veneer is actually needed. If you are using any architecture other than v4, the linker will most likely  convert a BL instruction to a BLX, avoiding the need for a veneer all together. The DUAL_STATE pragma and the -md option are ignored when using EABI.

  • 0 in reply to Cody Addison
    Genius 5660 points

    Hello Support,

    I understood BLX instruction will be inserted for the CALL to the function.

    But the destination THUMB function must return with BX LR instead of POP PC.

    I don't see that happening when I call from ARM to THUMB.

    Please help me understand if for Cortex-R4 option, POP PC return from THUMB is OK.
    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    Genius 5660 points

    Sorry, my mistake.

    In Cortex-R4, POP PC will change state based on Bit 0 and 1.

    Thank you.
    Regards
    Pashan