• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 54 subscribers
  • Views 2375 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Compiler: TMS320F28379_Test

serhii chekanov
Intellectual 640 points
Other Parts Discussed in Thread: TMS320F28379D

Tool/software: TI C/C++ Compiler

Hi! TI!

Could you help me with my problem.

"./source/F2837xD_struct.obj" "./source/F2837xD_usDelay.obj" "../F2837xD_Headers_nonBIOS_cpu1.cmd" "../TMS320F28379D.cmd" "../Lib/F021_API_F2837xD.lib" "../Lib/F021_API_F2837xD_FPU32.lib" "../Lib/IQmath.lib" "../Lib/IQmath_fpu32.lib" "../Lib/SFO_v8_fpu_lib_build_c28.lib" "../Lib/usblib.lib" -llibc.a ../LibSource/libc.a
<Linking>
error #10008-D: cannot find file "libc.a"
warning #10204-D: automatic RTS selection: could not resolve index library "libc.a" to a compatible library
warning #10208-D: automatic RTS selection: attempt to automatically link in index library "libc.a" failed; file not found
warning #10062-D: entry-point symbol "_c_int00" undefined
error #10010: errors encountered during linking; "HALO_TMS320F28379_Test.out" not built

My installs of linker

-v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 --advice:performance=all --define=CPU1 -g --diag_warning=225 --diag_wrap=off --display_error_number -z -m"HALO_TMS320F28379_Test.map" --stack_size=0x200 --warn_sections -i"C:/TMS320F28379_Test/TMS320F28379_Test/Lib" -i"C:/HALO_TMS320F28379_Test/HALO_TMS320F28379_Test" --reread_libs --diag_wrap=off --display_error_number --xml_link_info="HALO_TMS320F28379_Test_linkInfo.xml" --rom_model

  • 0
    Intellectual 640 points
    TMS320F28379D.cmd File is mod by me.

    MEMORY
    {
    PAGE 0 : /* Program Memory */
    /* BEGIN is used for the "boot to FLASH" bootloader mode */



    /* Flash boot address */


    //BEGIN : origin = 0x080000, length = 0x000002

    BEGIN_M0 : origin = 0x000040, length = 0x000002

    SIGN : origin = 0x080000, length = 0x000020

    BEGIN_FLASH : origin = 0x08007E, length = 0x000002
    FLASH : origin = 0x080080, length = 0x03FF7E /* summ on-chip FLASH */
    LSTART : origin = 0x0BFFFE, length = 0x000002



    LS05SARAM : origin = 0x008000, length = 0x003000

    D01SARAM : origin = 0x00B000, length = 0x001000


    BOOTROM : origin = 0x3F8000, length = 0x007000

    RAMGS56 : origin = 0x011000, length = 0x002000

    /* Flash sectors */
    // FLASHA : origin = 0x080080, length = 0x001F80 /* on-chip Flash */
    // FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
    // FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
    // FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
    // FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
    // FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
    // FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
    // FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
    // FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
    // FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
    // FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
    // FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
    // FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
    // FLASHN : origin = 0x0BE000, length = 0x001FFE /* on-chip Flash -2 on loader_Start */

    // RESET : origin = 0x3FFFC0, length = 0x000002



    PAGE 1 : /* Data Memory */

    // BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom
    // will use this for
    // stack */

    MSARAM : origin = 0x000000, length = 0x000800 /* on-chip RAM М0-М1 */
    // PIEVECT : origin = 0x000D00, length = 0x000200 /* PieVectTable 512W */
    // LS05SARAM : origin = 0x008000, length = 0x003000 /* on-chip RAM */

    /* on-chip Global shared RAMs */
    RAMGS04 : origin = 0x00C000, length = 0x005000 /* on-chip RAM + DMA */

    // RAMGS1 : origin = 0x00D000, length = 0x001000
    // RAMGS2 : origin = 0x00E000, length = 0x001000
    // RAMGS3 : origin = 0x00F000, length = 0x001000
    // RAMGS4 : origin = 0x010000, length = 0x001000


    // RAMGS5 : origin = 0x011000, length = 0x001000
    // RAMGS6 : origin = 0x012000, length = 0x001000 //


    DMA7RAMGS : origin = 0x013000, length = 0x001000
    // RAMGS7 : origin = 0x013000, length = 0x001000

    // RAMGS8 : origin = 0x014000, length = 0x001000
    // RAMGS9 : origin = 0x015000, length = 0x001000
    // RAMGS10 : origin = 0x016000, length = 0x001000
    // RAMGS11 : origin = 0x017000, length = 0x001000
    // RAMGS12 : origin = 0x018000, length = 0x001000
    // RAMGS13 : origin = 0x019000, length = 0x001000
    // RAMGS14 : origin = 0x01A000, length = 0x001000
    // RAMGS15 : origin = 0x01B000, length = 0x001000


    DD16 : origin = 0x80000000, length = 0x000001
    DD17 : origin = 0x80000001, length = 0x000001
    DD14 : origin = 0x80000100, length = 0x000001


    /* Shared MessageRam */



    CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
    CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
    }


    SECTIONS
    {
    /* Allocate program areas: */

    .cinit : > FLASH, PAGE = 0
    .pinit : > FLASH, PAGE = 0
    .binit : > FLASH, PAGE = 0
    .text : > FLASH, PAGE = 0
    codestart : > BEGIN_FLASH, PAGE = 0

    .stack : > MSARAM, PAGE = 1
    .cio : > RAMGS04, PAGE = 1


    .econst : > FLASH, PAGE = 0
    .switch : > FLASH, PAGE = 0
    .args : > FLASH, PAGE = 0


    FPUmathTables : > BOOTROM, PAGE = 0, TYPE = NOLOAD
    IQmathTables : > BOOTROM, PAGE = 0, TYPE = NOLOAD
    IQmath : > FLASH, PAGE = 0


    // .cinit : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHE |
    // FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ |
    // FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
    //
    //
    // .binit : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHE |
    // FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ |
    // FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
    //#ifdef __TI_EABI__
    // .init_array : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHE |
    // FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ |
    // FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
    //#else
    // .pinit : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHE |
    // FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ |
    // FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
    //#endif
    // .text : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHE |
    // FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ |
    // FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
    //
    // codestart : > BEGIN PAGE = 0




    /*** Section ramfuncs used by InitFlash() ".TI.ramfunc in Flash.c ***/
    secureRamFuncs : LOAD = FLASH, PAGE = 0
    RUN = LS05SARAM, PAGE = 0 /* must be CSM secured RAM */
    LOAD_START(_secureRamFuncs_loadstart),
    LOAD_END(_secureRamFuncs_loadend),
    RUN_START(_secureRamFuncs_runstart)
    ramfuncs : LOAD = FLASH, PAGE = 0
    RUN = LS05SARAM, PAGE = 0 /* must be CSM secured RAM */
    LOAD_START(_ramFuncs_loadstart),
    LOAD_END(_ramFuncs_loadend),
    RUN_START(_ramFuncs_runstart)

    {
    -l IQmath_fpu32.lib<IQ24sinPU.obj> (IQmath)
    -l IQmath_fpu32.lib<IQ24cosPU.obj> (IQmath)
    -l IQmath_fpu32.lib<IQ24rmpy.obj> (IQmath)
    -l IQmath_fpu32.lib<IQ24sqrt.obj> (IQmath)
    -l IQmath_fpu32.lib<IQ24div.obj> (IQmath)
    -l IQmath_fpu32.lib<IQ24atan2.obj> (IQmath)
    -l IQmath_fpu32.lib<IQ24sin.obj> (IQmath)
    -l IQmath_fpu32.lib<IQ24mag.obj> (IQmath)
    -l IQmath_fpu32.lib<IQ24toF.obj> (IQmath)
    -l IQmath_fpu32.lib<IQ24mpyI32int.obj> (IQmath)
    -l IQmath_fpu32.lib<IQ24atan2PU.obj> (IQmath)
    }

    SCIRamFunction : LOAD = FLASH, PAGE = 0
    RUN = LS05SARAM, PAGE = 0
    LOAD_START(_SCIRamFunction_loadstart),
    LOAD_END(_SCIRamFunction_loadend),
    RUN_START(_SCIRamFunction_runstart)

    SPIRamFunction : LOAD = FLASH, PAGE = 0
    RUN = LS05SARAM, PAGE = 0
    LOAD_START(_SPIRamFunction_loadstart),
    LOAD_END(_SPIRamFunction_loadend),
    RUN_START(_SPIRamFunction_runstart)
    //
    //
    //
    //
    //
    //
    // ramfuncs : LOAD = FLASHA | FLASHB | FLASHC | FLASHD | FLASHE |
    // FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ |
    // FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
    // RUN = LS05SARAM PAGE = 1
    // LOAD_START(_RamfuncsLoadStart),
    // LOAD_SIZE(_RamfuncsLoadSize),
    // LOAD_END(_RamfuncsLoadEnd),
    // RUN_START(_RamfuncsRunStart),
    // RUN_SIZE(_RamfuncsRunSize),
    // RUN_END(_RamfuncsRunEnd)



    sign : > SIGN, PAGE = 0
    loaderstart : > LSTART, PAGE = 0

    DMARAML4 : > RAMGS04, PAGE = 1 /
    m01saram : > LS05SARAM, PAGE = 0
    RAML34 : > RAMGS56, PAGE = 0

    DD14_IN : > DD14, PAGE = 1
    DD16_OUT : > DD16, PAGE = 1
    DD17_OUT : > DD17, PAGE = 1

    /* Non initiate */
    MySect : > RAMGS04, PAGE = 1



    .ebss: {
    _startEBSS = .; /
    *(.ebss)
    _endEBSS = .;
    } > RAMGS04 PAGE 1



    //#ifdef __TI_COMPILER_VERSION__
    //#if __TI_COMPILER_VERSION__ >= 15009000
    // .TI.ramfunc : {} LOAD = FLASH PAGE = 0,
    // RUN = LS05SARAM PAGE = 1,
    // table(BINIT)
    //#endif
    //#endif

    // /* Allocate uninitalized data sections: */
    // .stack : > M01SARAM | LS05SARAM PAGE = 1
    //#ifdef __TI_EABI__
    // .bss : > M01SARAM | LS05SARAM PAGE = 1
    // .sysmem : > LS05SARAM | M01SARAM PAGE = 1
    // .data : > M01SARAM | LS05SARAM PAGE = 1
    //#else
    // .ebss : > M01SARAM | LS05SARAM PAGE = 1
    // .esysmem : > LS05SARAM | M01SARAM PAGE = 1
    //#endif
    // .cio : > LS05SARAM | M01SARAM PAGE = 1

    /* Initalized sections go in Flash */
    //#ifdef __TI_EABI__
    // .const : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHE |
    // FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ |
    // FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
    //#else
    // .econst : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHE |
    // FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ |
    // FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
    //#endif
    // .switch : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHE |
    // FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ |
    // FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
    // .args : > FLASHA | FLASHB | FLASHC | FLASHD | FLASHE |
    // FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ |
    // FLASHK | FLASHL | FLASHM | FLASHN PAGE = 0
    //
    // .reset : > FLASH, PAGE = 0, TYPE = DSECT /* not used, */

    Filter_RegsFile : > RAMGS04, PAGE = 1

    /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
    PUTBUFFER
    PUTWRITEIDX
    GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
    GETBUFFER : TYPE = DSECT
    GETWRITEIDX : TYPE = DSECT
    PUTREADIDX : TYPE = DSECT
    }
    }
    /*End of file*/
  • 0
    Guru 26200 points

    Hi,

    serhii chekanov said:
    "./source/F2837xD_struct.obj" "./source/F2837xD_usDelay.obj" "../F2837xD_Headers_nonBIOS_cpu1.cmd" "../TMS320F28379D.cmd" "../Lib/F021_API_F2837xD.lib" "../Lib/F021_API_F2837xD_FPU32.lib" "../Lib/IQmath.lib" "../Lib/IQmath_fpu32.lib" "../Lib/SFO_v8_fpu_lib_build_c28.lib" "../Lib/usblib.lib" -llibc.a ../LibSource/libc.a

    You link libc.a twice: -llibc.a ../LibSource/libc.a
    Delete the last one and try. 

  • 0
    TI__Guru**** 251100 points

    In addition to removing this second libc.a ...

    serhii chekanov said:
    ../LibSource/libc.a

    I don't see where you refer to the compiler include and lib directories.  A typical CCS project for a C28x processor has linker file search paths as shown in the screen shot below.  After the variables are replaced, this comes to something like ...

    -i"C:/ti/ccsv8/tools/compiler/ti-cgt-c2000_18.1.2.LTS/lib"
-i"C:/ti/ccsv8/tools/compiler/ti-cgt-c2000_18.1.2.LTS/include"

    The file libc.a is in the lib directory given by that -i option.  You need to do the same thing in your build.

    Thanks and regards,

    -George

  • 0 in reply to Tomasz Kocon
    Intellectual 640 points

    That right! Thank You!