CCS/TMS320F28377D: How can I chose the exact address order for CPU1 and CPU2 vars in SGRAM when binding them with prama directive ?

Diego Bellachioma

Part Number: TMS320F28377D

Tool/software: Code Composer Studio

Hi.

I need to match address shared var when binding them using pragma directive between CPU in the same chip; for now I obtain a causale order by linker. Follow, I report code that I'm using:

Var_CPU1.h

uint16_t mIPFC_W, mIC1PFC, mIC2PFC, mIC3PFC, mEMVOUT_U, mEMVOUT_V, mEMVOUT_W, mIL1_DCDC, mIL2_DCDC, mIPFC_U, mIPFC_V, mPFCVIN_U, mPFCVIN_V, mPFCVIN_W;
#pragma DATA_SECTION(mIPFC_W,"SHARERAMGS15");
#pragma DATA_SECTION(mIC1PFC,"SHARERAMGS15");
#pragma DATA_SECTION(mIC2PFC,"SHARERAMGS15");
#pragma DATA_SECTION(mIC3PFC,"SHARERAMGS15");
#pragma DATA_SECTION(mEMVOUT_U,"SHARERAMGS14");
#pragma DATA_SECTION(mEMVOUT_V,"SHARERAMGS14");
#pragma DATA_SECTION(mEMVOUT_W,"SHARERAMGS14");

Var_CPU2.h

uint16_t mIPFC_W, mIC1PFC, mIC2PFC, mIC3PFC, mEMVOUT_U, mEMVOUT_V, mEMVOUT_W, mIINV_U, mIINV_V, mIINV_W, mIINV_N, mINVOUT_U, mINVOUT_V, mINVOUT_W;
#pragma DATA_SECTION(mIPFC_W,"SHARERAMGS15");
#pragma DATA_SECTION(mIC1PFC,"SHARERAMGS15");
#pragma DATA_SECTION(mIC2PFC,"SHARERAMGS15");
#pragma DATA_SECTION(mIC3PFC,"SHARERAMGS15");
#pragma DATA_SECTION(mEMVOUT_U,"SHARERAMGS14");
#pragma DATA_SECTION(mEMVOUT_V,"SHARERAMGS14");
#pragma DATA_SECTION(mEMVOUT_W,"SHARERAMGS14");

and this is CPU's map result:

How Can I matching var address ? Is there an easy way to tell that to linker ?

Follow, I report cmd file section:

...
   // USED TO SHARE DATA BETWEEN CPU1&CPU2
   RAMGS14          : origin = 0x01A000, length = 0x001000     	/* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x001000     	/* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
...
   // DATA EXCHANGE BETWEEN CPU
   SHARERAMGS14		: > RAMGS14,	PAGE = 0     	/* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   SHARERAMGS15		: > RAMGS15,	PAGE = 0
...

Maybe, I must specify single var linker section with exact origin address and length for each var; this approach seems me very strange.

Thanks a lot for your help.

over 6 years ago

0 George Mock over 6 years ago

TI__Guru**** 250440 points

The only way to completely control how variables are laid out in memory is to define them in hand-coded assembly. That may sound difficult, but it is not that hard. Please follow a procedure similar to the following.

Add the compiler option --src_interlist. This option tells the compiler to keep the auto-generated assembly files, rather than delete them. In addition, comments are added which make the assembly code easier to understand. The file has the same name as the source file, with the extension changed to .asm.

Build one source file which defines the global variables of interest. Inspect the resulting assembly file. Note how the assembler directives .usect and .global are used. Read about those directives in the C28x assembly tools manual.

Now you are ready to write your hand-coded assembly file. The global variables will be in the same order as the source. Add the assembly file to the CCS project, just like any other source file.

In your linker command file, you can allocate the variables to the desired location with syntax similar to ...

    .shared_variables > 0x1234

This creates an output section named .shared_variables. Change this name to whatever section name you use in the assembly file. It collects together all of the input sections named .shared_variables. In this case, there is only one input section with that name, which comes from the assembly file. Change 0x1234 to the desired address.

Thanks and regards,

-George

0 Diego Bellachioma over 6 years ago in reply to George Mock

Intellectual 500 points

Hi George.

Thanks a lot for your advice. Meanwhile, I tried to force var address biding using struct allocation. Anyway, I want to testing your procedure.

Have a nice day : )

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CCS/TMS320F28377D: How can I chose the exact address order for CPU1 and CPU2 vars in SGRAM when binding them with prama directive ?