CCS/CCSTUDIO: memory alignment problem

Andy Lin94

Expert 1390 points

Part Number: CCSTUDIO
Other Parts Discussed in Thread: AM3352

Tool/software: Code Composer Studio

ide: ccs8.2.0

compiler ti v5.2.5

chip: am3352

image: https://imgur.com/a/c1NJ0ZV

1. I created a struct rxBuf_s

2. I create a ptr rxBuf_p and assign it with address of rxBuf at line 235( rxBuf is an array with size 1504 byte)

3. The first member stx is aligned to address 0x8030331C, which is I expected

But, why pktlen_u is aligned to 0x8030331"E"? The member stx is only 1 byte.

Is this implying that the minimum memory size this chip can access is 2 bytes? Not 1 byte?

Also, I tried this scenario.

typedef struct{

u8 a;

u8 b;

}test;

The memory allocation in this scenario is contiguous. I think this chip can access memory with 8-bit space.

This phenomenal is mysterious to me. What background knowledge do I miss?

Thank you.

over 6 years ago

0 Hnz over 6 years ago

Guru 39650 points

Hi,

I did not use am3352 (Cortex-A8) but is pretty normal that structures are aligned at 16bit/32bit/64bit cores. Properly aligned structures allows to optimal memory access. Structure alignment can be disabled by macro #pragma pack.

See Wiki about alignment of structures en.wikipedia.org/.../Data_structure_alignment

Jan

0 Chester Gillon over 6 years ago

Guru 92251 points

Bu default the compiler will align structure fields, which can insert implicit padding into the structure.

The attached example compiled for an AM335x using TI ARM compiler v5.2.5 has two structures with the same fields but:

a. rxBuf_nopack has no packing specified, and the compiler has inserted padding.

b. rxBuf_packed uses __attribute__((__packed__)) to disabling padding.

The following output from the program shows that the packed structure doesn't have padding:

[CortxA8] sizeof(nopack)=6
&nopack.stx=0x40305948
&nopack.pktlen=0x4030594a
&nopack.pid=0x4030594c
sizeof(packed)=4
&packed.stx=0x40305950
&packed.pktlen=0x40305951
&packed.pid=0x40305953

Note that because the example is a bare-metal example which doesn't enable the MMU the "Generate unaligned loads and stores (--unaligned access)" compiler option had to set to off. This is because with the MMU disabled the packed.pktlen = 5; statement caused the program to fail with an "alignment fault" data abort when an unaligned 16-bit store was attempted. As explained in Unaligned Access on AM335x:

Even with strict alignment checking disabled, unaligned access is only supported to normal-type memory (as opposed to device or strongly-ordered). This means in particular you need to configure and enable the MMU since all data access is strongly-ordered while the MMU is disabled.

AM3359_struct_padding.zip

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CCS/CCSTUDIO: memory alignment problem