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Compiler: CCS5.5.0

Tool/software: TI C/C++ Compiler

Dear all,

I'm working on the dsp6678 board, and I'm analyzing examples of dynamic loading from core 0 to core 1

The main routine of this code is the following 

Using the debugger I noticed that the code enters only in the the branch that is related with the core 0 and never in the branch that is related with core1.

Somebodycan help me.

#include <xdc/std.h>
#include <stdio.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>

#define DEF_INIT_CONFIG_PLL1_PLLM 0
#define DEF_INT_MEM_TEST_CORE_ID 1
#define MAGIC_ADDR 0x8ffffc
#define DEVICE_REG32_W(x,y) *(volatile uint32_t *)(x)=(y)
#define DEVICE_REG32_R(x) (*(volatile uint32_t *)(x))
#define BOOT_MAGIC_ADDR(x) (MAGIC_ADDR + (1<<28) + (x<<24))
#define STATUS_ADDR (MAGIC_ADDR - 0x4)


#define CHIP_LEVEL_REG 0x02620000
#define KICK0 (CHIP_LEVEL_REG + 0x0038)
#define KICK1 (CHIP_LEVEL_REG + 0x003C)
#define IPCGR(x) (0x02620240 + x*4)

#define BOOT_MAGIC_NUMBER 0xBABEFACE
extern __cregister volatile unsigned int DNUM;

void write_boot_magic_number(void)
{
    printf("core %d\n",DNUM);
    DEVICE_REG32_W(MAGIC_ADDR, BOOT_MAGIC_NUMBER);

    while(1);
}

/******************************************************************************
* Function: main
******************************************************************************/
int main ()
{
    int coreNum;
    int core=0;


    /* Unlock the chip registers */
    DEVICE_REG32_W(KICK0, 0x83e70b13);
    DEVICE_REG32_W(KICK1, 0x95a4f1e0);

    //coreNum = platform_get_coreid();
    coreNum=DNUM;
    if (coreNum == 0)
    {
        /* Writing the entry address to other cores */
        printf("core0\n");
        for (core = 1; core < 8; core++)
        {
            DEVICE_REG32_W(BOOT_MAGIC_ADDR(core), (uint32_t)write_boot_magic_number);
        }
        for (core = 1; core < 8; core++)
        {
            DEVICE_REG32_W(IPCGR(core), 1);
       }
    }
    else
    {
        write_boot_magic_number();
    }

    return 0;
}

  • Hello Tian yang,

    What was the exact issue? Core 1 is not running? What is the PC value when you connect emulator to Core 1? Core 0 is supposed to bring core 1 & other cores out of reset during the ROM bootloader sequence.

    Note when you debug bootloader issues, in your CCS set up, the GEL file needs to be removed so it doesn't impact the behavior.

    best regards,
    David Zhou
  • Hi,

    Please follow steps from below e2e post,

    Thank you.