To set watchdog Timeout interval, we use the following sequence of steps :
1) 24MHz/512/x = y Hz (OSCCLK/512/x) (where x = 1,2,4,8,16,32,64 => lesser the value of x, less Timeout interval)
2) Inverse y so that frequency is expressed in Seconds
(T = 1 / f )
3) Multiply inversed y with watchdog register size, i.e., if it's a 8 bits register, multiply with 256.
4) Minimally i will get 5.46 mSeconds
I want this timeout interval reduce to 1.5 mSeconds
Following information may help you
WDPS Watchdog pre-scale. These bits configure the watchdog counter clock (WDCLK) rate relative
to OSCCLK/512:
000 WDCLK = OSCCLK/512/1 (default)
001 WDCLK = OSCCLK/512/1
010 WDCLK = OSCCLK/512/2
011 WDCLK = OSCCLK/512/4
100 WDCLK = OSCCLK/512/8
101 WDCLK = OSCCLK/512/16
110 WDCLK = OSCCLK/512/32
111 WDCLK = OSCCLK/512/64