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Compiler/TMS320TCI6484: Relocation Table 1/1 for Section ".debug_line" is different in each build

Part Number: TMS320TCI6484
Other Parts Discussed in Thread: CCSTUDIO

Tool/software: TI C/C++ Compiler

Hi, 

for example, when I compile a c file to object file, the relocation parts in output object files in two generations as bellow, you may notice the DDR_CODE sections are listed at the top in one build, but in another build, they are listed in last part. This difference occurs in obj file, but leads to the final lib files, .out files are also different.  Our customer requests us to release same binaries based on the same code and build environment, this is why I ask to solve this problem.

Then I narrowed down the problem, I found that the intermediate file xxxxx11 file in temp directory is always the same, bu the the output object file produced by asm6x.exe are different.  Could anyone tell me what's the root cause in asm6x.exe make this difference? And how to fix it?

The building tool is C6000 Code Generation Tools 6.0.23.

Relocation Table 1/1 for Section ".debug_line"

id type offset addend symbol
-- ---- ------ ------ ------
0 RM_DWARF_LENGTH 0x00000000 0 N/A
1 RM_OBJ 0x0000008c 0 .DDR_CODE
2 RM_RANGE 0x0000008c 0 N/A
3 R_RELLONG 0x0000008f 0 .DDR_CODE
4 R_RELLONG 0x000000ab 0 .DDR_CODE
5 RM_OBJ 0x000000e2 0 .text
6 RM_RANGE 0x000000e2 0 N/A
7 R_RELLONG 0x000000e5 0 .text
8 R_RELLONG 0x000000fb 0 .text
9 R_RELLONG 0x00000112 0 .text
10 R_RELLONG 0x0000012a 0 .text
11 R_RELLONG 0x00000147 0 .text
12 R_RELLONG 0x00000166 0 .text
13 R_RELLONG 0x0000017c 0 .text
14 R_RELLONG 0x00000192 0 .text
15 R_RELLONG 0x000001a9 0 .text
16 R_RELLONG 0x000001c3 0 .text
17 R_RELLONG 0x000001eb 0 .text
18 R_RELLONG 0x00000201 0 .text
19 R_RELLONG 0x00000219 0 .text
20 R_RELLONG 0x00000249 0 .text

Relocation Table 1/1 for Section ".debug_line"

id type offset addend symbol
-- ---- ------ ------ ------
0 RM_DWARF_LENGTH 0x00000000 0 N/A
1 RM_OBJ 0x0000008c 0 .text
2 RM_RANGE 0x0000008c 0 N/A
3 R_RELLONG 0x0000008f 0 .text
4 R_RELLONG 0x000000a5 0 .text
5 R_RELLONG 0x000000bc 0 .text
6 R_RELLONG 0x000000d4 0 .text
7 R_RELLONG 0x000000f1 0 .text
8 R_RELLONG 0x00000110 0 .text
9 R_RELLONG 0x00000126 0 .text
10 R_RELLONG 0x0000013c 0 .text
11 R_RELLONG 0x00000153 0 .text
12 R_RELLONG 0x0000016d 0 .text
13 R_RELLONG 0x00000195 0 .text
14 R_RELLONG 0x000001ab 0 .text
15 R_RELLONG 0x000001c3 0 .text
16 R_RELLONG 0x000001f3 0 .text
17 RM_OBJ 0x00000218 0 .DDR_CODE
18 RM_RANGE 0x00000218 0 N/A
19 R_RELLONG 0x0000021b 0 .DDR_CODE
20 R_RELLONG 0x00000237 0 .DDR_CODE

  • user5950885 said:
    Our customer requests us to release same binaries based on the same code and build environment

    TI does not guarantee that behavior.  For further detail, please see this forum thread.

    Speaking generally,instead of expecting binaries to be identical, it is better to compare object files and executables with the utility objdiff from the cg_xml package.  By default, objdiff ignores the debug sections like .debug_line.  This particular difference would not be noticed.  After all, it has no impact on system execution. While anything it is possible, it is very likely this difference has no impact on the debug experience.

    All that said, I am happy to help you understand how this happened.  We need to reproduce it.  I presume the problem object file starts out as a C or C++ source file.  For that file, please follow the directions in the article How to Submit a Compiler Test Case.  In addition, I need some clue, any clue, on what you do that somehow causes the difference in the .debug_line section.  Is your host system Windows 10, Linux, or what?  

    Thanks and regards,

    -George

  • Hi, George:

    Here is my build information, on Windows Server 2012 R2.

    ;******************************************************************************
    ;* TMS320C6x C/C++ Codegen PC v6.0.23 *
    ;* Date/Time created: Tue Oct 30 17:31:03 2018 *
    ;******************************************************************************
    .compiler_opts --c64p_l1d_workaround=default --endian=big --hll_source=on --mem_model:code=near --mem_model:data=far_aggregates --silicon_version=6500 --symdebug:skeletal

    ;******************************************************************************
    ;* GLOBAL FILE PARAMETERS *
    ;* *
    ;* Architecture : TMS320C64x+ *
    ;* Optimization : Enabled at level 2 *
    ;* Optimizing for : Speed *
    ;* Based on options: -o2, no -ms *
    ;* Endian : Big *
    ;* Interrupt Thrshld : Disabled *
    ;* Data Access Model : Far Aggregate Data *
    ;* Pipelining : Enabled *
    ;* Speculate Loads : Disabled *
    ;* Memory Aliases : Presume are aliases (pessimistic) *
    ;* Debug Info : DWARF Debug for Program Analysis w/Optimization *
    ;* *
    ;******************************************************************************

    Here are some clues:
    Actually, the different part is debug information, we tried to use option --symdebug:none to eliminate the debug information, but a link error occured and caused the make failed. I think it is more difficult to find out the root cause of the link error. So I decide to solve this problem first.

    Compiling tools put the information which are in the same section into same block, but the position is uncertain. I noticed that asm6x.exe and ofd6x.exe have the same behavior. Asm6x produces different obj file from same intermediate file, ofd6x.exe produces different xml file from the same .out file. When you reproduce this scenario, please try serveral times, it is not happen every time.

    It looks there is a mechamism to make the ouput order. I think you make to reproduce with ofd6x on a .out file on your side.

    1. The following table of an object file produced by asm6x.exe. The "DDR_CODE" lines are on the bottom, or on the top.

    One build:

    Relocation Table 1/1 for Section ".debug_line"

    id type offset addend symbol
    -- ---- ------ ------ ------
    0 RM_DWARF_LENGTH 0x00000000 0 N/A
    1 RM_OBJ 0x0000008c 0 .text
    2 RM_RANGE 0x0000008c 0 N/A
    3 R_RELLONG 0x0000008f 0 .text
    4 R_RELLONG 0x000000a5 0 .text
    5 R_RELLONG 0x000000bc 0 .text
    6 R_RELLONG 0x000000d4 0 .text
    7 R_RELLONG 0x000000f1 0 .text
    8 R_RELLONG 0x00000110 0 .text
    9 R_RELLONG 0x00000126 0 .text
    10 R_RELLONG 0x0000013c 0 .text
    11 R_RELLONG 0x00000153 0 .text
    12 R_RELLONG 0x0000016d 0 .text
    13 R_RELLONG 0x00000195 0 .text
    14 R_RELLONG 0x000001ab 0 .text
    15 R_RELLONG 0x000001c3 0 .text
    16 R_RELLONG 0x000001f3 0 .text
    17 RM_OBJ 0x00000218 0 .DDR_CODE
    18 RM_RANGE 0x00000218 0 N/A
    19 R_RELLONG 0x0000021b 0 .DDR_CODE
    20 R_RELLONG 0x00000237 0 .DDR_CODE


    Another build:

    Relocation Table 1/1 for Section ".debug_line"

    id type offset addend symbol
    -- ---- ------ ------ ------
    0 RM_DWARF_LENGTH 0x00000000 0 N/A
    1 RM_OBJ 0x0000008c 0 .DDR_CODE
    2 RM_RANGE 0x0000008c 0 N/A
    3 R_RELLONG 0x0000008f 0 .DDR_CODE
    4 R_RELLONG 0x000000ab 0 .DDR_CODE
    5 RM_OBJ 0x000000e2 0 .text
    6 RM_RANGE 0x000000e2 0 N/A
    7 R_RELLONG 0x000000e5 0 .text
    8 R_RELLONG 0x000000fb 0 .text
    9 R_RELLONG 0x00000112 0 .text
    10 R_RELLONG 0x0000012a 0 .text
    11 R_RELLONG 0x00000147 0 .text
    12 R_RELLONG 0x00000166 0 .text
    13 R_RELLONG 0x0000017c 0 .text
    14 R_RELLONG 0x00000192 0 .text
    15 R_RELLONG 0x000001a9 0 .text
    16 R_RELLONG 0x000001c3 0 .text
    17 R_RELLONG 0x000001eb 0 .text
    18 R_RELLONG 0x00000201 0 .text
    19 R_RELLONG 0x00000219 0 .text
    20 R_RELLONG 0x00000249 0 .text

    2. From the same .out file, run "C:\buildtools\CCStudio_v3.3\C6000\cgtools\bin>ofd6x.exe -g -o=BESA_DSP_CORE0.xml BESA_DSP_CORE0.out" to produce xml files and compare:

    Produce 1:

    --------------------------------------
    Line Number Program at Offset 00003d59
    --------------------------------------


    Header Information


    Length: 617
    Version: 2
    Header Length: 130
    Minimum Instruction Length: 2
    Default is_stmt: true
    Line Base: 0
    Line Range: 10
    Opcode Base: 10
    Standard Opcode Lengths: { 1, 1, 1, 1, 0, 0, 0, 0, 0 }


    Include Directories


    id name
    -- ----
    0 (unknown)


    Files


    id name directory last mod length
    -- ---- --------- --------- ---------
    0 (unknown) 0 (unknown) (unknown)
    1 ..\..\src\MIMO\bcu\src\pfdsp\src\BESA_DSP_SCH_PF.c 0 (unknown) (unknown)
    2 ..\..\src\MIMO\bcu\src\pfdsp\include\BESA_DSP_COMM_CDT.h 0 (unknown) (unknown)


    Line Number Program


    address file line col S B section
    ---------- ---- ---- --- - - -------
    0x815575e0 1 2233 1 Y N .DDR_CODE
    0x8155763c 1 2243 0 Y N .DDR_CODE
    0x81557640 1 2245 0 Y N .DDR_CODE
    0x81557814 1 2318 0 Y N .DDR_CODE
    0x81557818 1 2318 0 Y N .DDR_CODE (end)
    0x81557818 1 2440 1 Y N .DDR_CODE
    0x8155786c 1 2479 0 Y N .DDR_CODE
    0x81557880 1 2480 0 Y N .DDR_CODE
    0x81557900 1 2413 0 Y N .DDR_CODE
    0x8155790c 1 2414 0 Y N .DDR_CODE
    0x8155792e 1 2416 0 Y N .DDR_CODE
    0x81557974 1 2506 0 Y N .DDR_CODE
    0x815579f4 1 2413 0 Y N .DDR_CODE
    0x815579f8 1 2414 0 Y N .DDR_CODE
    0x81557a40 1 2416 0 Y N .DDR_CODE
    0x81557a90 1 2538 13 Y N .DDR_CODE
    0x81557a94 1 2538 13 Y N .DDR_CODE (end)
    0x00833020 1 209 1 Y N .text
    0x008330ec 1 268 1 Y N .text
    0x008330f4 1 268 1 Y N .text (end)
    0x008330f4 1 271 1 Y N .text
    0x008333d4 1 335 1 Y N .text
    0x008333dc 1 335 1 Y N .text (end)
    0x008333dc 1 2336 1 Y N .text
    0x008334e0 1 2386 13 Y N .text
    0x008334e4 1 2386 13 Y N .text (end)
    0x008334e4 1 2098 1 Y N .text
    0x0083354c 1 2115 0 Y N .text
    0x0083354e 1 2117 0 Y N .text
    0x00833818 1 2211 0 Y N .text
    0x00833820 1 2211 0 Y N .text (end)

    ...<a long list of .text, to the end>

    Produce 2:

    --------------------------------------
    Line Number Program at Offset 00003d59
    --------------------------------------

    Header Information

    Length: 617
    Version: 2
    Header Length: 130
    Minimum Instruction Length: 2
    Default is_stmt: true
    Line Base: 0
    Line Range: 10
    Opcode Base: 10
    Standard Opcode Lengths: { 1, 1, 1, 1, 0, 0, 0, 0, 0 }

    Include Directories

    id name
    -- ----
    0 (unknown)

    Files

    id name directory last mod length
    -- ---- --------- --------- ---------
    0 (unknown) 0 (unknown) (unknown)
    1 ..\..\src\MIMO\bcu\src\pfdsp\src\BESA_DSP_SCH_PF.c 0 (unknown) (unknown)
    2 ..\..\src\MIMO\bcu\src\pfdsp\include\BESA_DSP_COMM_CDT.h 0 (unknown) (unknown)

    Line Number Program

    address file line col S B section
    ---------- ---- ---- --- - - -------
    0x00833020 1 209 1 Y N .text
    0x008330ec 1 268 1 Y N .text
    0x008330f4 1 268 1 Y N .text (end)
    0x008330f4 1 271 1 Y N .text
    0x008333d4 1 335 1 Y N .text
    0x008333dc 1 335 1 Y N .text (end)
    0x008333dc 1 2336 1 Y N .text
    0x008334e0 1 2386 13 Y N .text
    0x008334e4 1 2386 13 Y N .text (end)

    ...<a long list of .text>

    0x815575e0 1 2233 1 Y N .DDR_CODE
    0x8155763c 1 2243 0 Y N .DDR_CODE
    0x81557640 1 2245 0 Y N .DDR_CODE
    0x81557814 1 2318 0 Y N .DDR_CODE
    0x81557818 1 2318 0 Y N .DDR_CODE (end)
    0x81557818 1 2440 1 Y N .DDR_CODE
    0x8155786c 1 2479 0 Y N .DDR_CODE
    0x81557880 1 2480 0 Y N .DDR_CODE
    0x81557900 1 2413 0 Y N .DDR_CODE
    0x8155790c 1 2414 0 Y N .DDR_CODE
    0x8155792e 1 2416 0 Y N .DDR_CODE
    0x81557974 1 2506 0 Y N .DDR_CODE
    0x815579f4 1 2413 0 Y N .DDR_CODE
    0x815579f8 1 2414 0 Y N .DDR_CODE
    0x81557a40 1 2416 0 Y N .DDR_CODE
    0x81557a90 1 2538 13 Y N .DDR_CODE
    0x81557a94 1 2538 13 Y N .DDR_CODE (end)
    <end of the table>

    Best regard,

    Jim

  • It appears you meant to attach a CCS project, or something.  However, I don't see any attachment.  It would best if you submitted one source file, along with all other details, described in the article How to Submit a Compiler Test Case.

    Thanks and regards,

    -George

  • Please submit the requested test case.

    Thanks and regards,

    -George

  • Since it has been while, I presume you have resolved your problem.  I'd appreciate hearing how you resolved it.

    Thanks and regards,

    -George

  • Hi, George,

        The "--symdebug:none " option can suppress symbolic debug generation which cause the differentiation. But some projects link failed. Then you tell me use "--gen_func_subsections" to find the increased size of functions. Yes, I found some, and then we move some of them to other sections which have available room .  

    So, the problem fixed.

    thanks for your help.