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CCS/TMS320VC5502: XDS100V2

Muneeswaran manokaran
Intellectual 650 points
Part Number: TMS320VC5502


Tool/software: Code Composer Studio

Hi,

I am using custom design XDS100v2 (TI reference design).While, i will connect target board i am getting following message:

C55xx: GEL: Error while executing OnReset(0): Memory verification failed at address 0x80D

       at GEL_MemoryFill(0x80D, 2, 1, 0x4748) [c5502.gel:202]

       at Init_CE0_SDRAM_5502CPUBoard() [c5502.gel:66]

       at OnReset(0)

C55xx: GEL Output: C5502_Init Complete.

C55xx: GEL: Error while executing OnTargetConnect(): Memory verification failed at address 0x80D

       at GEL_MemoryFill(0x80D, 2, 1, 0x4748) [c5502.gel:202]

       at Init_CE0_SDRAM_5502CPUBoard() [c5502.gel:60]

       at OnTargetConnect()

Anybody have solution for rectify above probelm.

thanks in advance

  • 0
    TI__Guru**** 472211 points

    Hello,

    There error is a common one and documented in detail in the below article:

    http://software-dl.ti.com/ccs/esd/documents/troubleshooting-data_verification_errors.html

    Basically the memory fill is having issues writing correct values to 0x80D (EMIF_SDCNT2). You mention you are using a custom made XDS100v2. Have you tried using it with a standard (non-custom) XDS100v2, does the error still occur?

    Thanks

    ki

  • 0 in reply to Ki
    Intellectual 650 points

    Hi ,

    Yesterday my XDS100v2 board connected , got message while test connection

    [Start: Texas Instruments XDS100v2 USB Debug Probe_0]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]

    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\YEPL\AppData\Local\TEXASI~1\CCS\

       ti\1\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 100- or 510-class product.

    This utility will load the adapter 'jioserdesusb.dll'.

    The library build date was 'Mar 13 2019'.

    The library build time was '21:35:20'.

    The library package version is '8.1.0.00005'.

    The library component version is '35.35.0.0'.

    The controller does not use a programmable FPGA.

    The controller has a version number of '4' (0x00000004).

    The controller has an insertion length of '0' (0x00000000).

    This utility will attempt to reset the controller.

    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.

    The controller is the FTDI FT2232 with USB interface.

    The link from controller to target is direct (without cable).

    The software is configured for FTDI FT2232 features.

    The controller cannot monitor the value on the EMU[0] pin.

    The controller cannot monitor the value on the EMU[1] pin.

    The controller cannot control the timing on output pins.

    The controller cannot control the timing on input pins.

    The scan-path link-delay has been set to exactly '0' (0x0000).

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    There is no hardware for programming the JTAG TCLK frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    There is no hardware for measuring the JTAG TCLK frequency.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 64 32-bit words.

    The test for the JTAG IR instruction path-length succeeded.

    The JTAG IR instruction path-length is 38 bits.

    The test for the JTAG DR bypass path-length succeeded.

    The JTAG DR bypass path-length is 1 bits.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 64 32-bit words.

    This test will be applied just once.

    Do a test using 0xFFFFFFFF.

    Scan tests: 1, skipped: 0, failed: 0

    Do a test using 0x00000000.

    Scan tests: 2, skipped: 0, failed: 0

    Do a test using 0xFE03E0E2.

    Scan tests: 3, skipped: 0, failed: 0

    Do a test using 0x01FC1F1D.

    Scan tests: 4, skipped: 0, failed: 0

    Do a test using 0x5533CCAA.

    Scan tests: 5, skipped: 0, failed: 0

    Do a test using 0xAACC3355.

    Scan tests: 6, skipped: 0, failed: 0

    All of the values were scanned correctly.

    The JTAG IR Integrity scan-test has succeeded.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 64 32-bit words.

    This test will be applied just once.

    Do a test using 0xFFFFFFFF.

    Scan tests: 1, skipped: 0, failed: 0

    Do a test using 0x00000000.

    Scan tests: 2, skipped: 0, failed: 0

    Do a test using 0xFE03E0E2.

    Scan tests: 3, skipped: 0, failed: 0

    Do a test using 0x01FC1F1D.

    Scan tests: 4, skipped: 0, failed: 0

    Do a test using 0x5533CCAA.

    Scan tests: 5, skipped: 0, failed: 0

    Do a test using 0xAACC3355.

    Scan tests: 6, skipped: 0, failed: 0

    All of the values were scanned correctly.

    The JTAG DR Integrity scan-test has succeeded.

    [End: Texas Instruments XDS100v2 USB Debug Probe_0]

    Today i connect same board , got message while Test connection

    [Start: Texas Instruments XDS100v2 USB Debug Probe_0]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]

    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\YEPL\AppData\Local\TEXASI~1\CCS\

       ti\1\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 100- or 510-class product.

    This utility will load the adapter 'jioserdesusb.dll'.

    The library build date was 'Mar 13 2019'.

    The library build time was '21:35:20'.

    The library package version is '8.1.0.00005'.

    The library component version is '35.35.0.0'.

    The controller does not use a programmable FPGA.

    The controller has a version number of '4' (0x00000004).

    The controller has an insertion length of '0' (0x00000000).

    This utility will attempt to reset the controller.

    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.

    The controller is the FTDI FT2232 with USB interface.

    The link from controller to target is direct (without cable).

    The software is configured for FTDI FT2232 features.

    The controller cannot monitor the value on the EMU[0] pin.

    The controller cannot monitor the value on the EMU[1] pin.

    The controller cannot control the timing on output pins.

    The controller cannot control the timing on input pins.

    The scan-path link-delay has been set to exactly '0' (0x0000).

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    There is no hardware for programming the JTAG TCLK frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    There is no hardware for measuring the JTAG TCLK frequency.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 64 32-bit words.

    The test for the JTAG IR instruction path-length failed.

    The JTAG IR instruction scan-path is stuck-at-zero.

    The test for the JTAG DR bypass path-length failed.

    The JTAG DR bypass scan-path is stuck-at-zero.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 64 32-bit words.

    This test will be applied just once.

    Do a test using 0xFFFFFFFF.

    Test 1 Word 0: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 1: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 2: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 3: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 4: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 5: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 6: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 7: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    The details of the first 8 errors have been provided.

    The utility will now report only the count of failed tests.

    Scan tests: 1, skipped: 0, failed: 1

    Do a test using 0x00000000.

    Scan tests: 2, skipped: 0, failed: 1

    Do a test using 0xFE03E0E2.

    Scan tests: 3, skipped: 0, failed: 2

    Do a test using 0x01FC1F1D.

    Scan tests: 4, skipped: 0, failed: 3

    Do a test using 0x5533CCAA.

    Scan tests: 5, skipped: 0, failed: 4

    Do a test using 0xAACC3355.

    Scan tests: 6, skipped: 0, failed: 5

    Some of the values were corrupted - 83.3 percent.

    The JTAG IR Integrity scan-test has failed.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 64 32-bit words.

    This test will be applied just once.

    Do a test using 0xFFFFFFFF.

    Test 1 Word 0: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 1: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 2: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 3: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 4: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 5: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 6: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    Test 1 Word 7: scanned out 0xFFFFFFFF and scanned in 0x00000000.

    The details of the first 8 errors have been provided.

    The utility will now report only the count of failed tests.

    Scan tests: 1, skipped: 0, failed: 1

    Do a test using 0x00000000.

    Scan tests: 2, skipped: 0, failed: 1

    Do a test using 0xFE03E0E2.

    Scan tests: 3, skipped: 0, failed: 2

    Do a test using 0x01FC1F1D.

    Scan tests: 4, skipped: 0, failed: 3

    Do a test using 0x5533CCAA.

    Scan tests: 5, skipped: 0, failed: 4

    Do a test using 0xAACC3355.

    Scan tests: 6, skipped: 0, failed: 5

    Some of the values were corrupted - 83.3 percent.

    The JTAG DR Integrity scan-test has failed.

    [End: Texas Instruments XDS100v2 USB Debug Probe_0]

    Anybody know about this problem?

    Problem in my hardware or any-other setup?

    My board customised design TI reference design(attached)...

    (i dont have non-custom XDS100V2 Emulator)xds100v2schematic.pdf

  • 0 in reply to Muneeswaran manokaran
    TI__Guru**** 472211 points

    Muneeswaran manokaran said:

    This path-length test uses blocks of 64 32-bit words.

    The test for the JTAG IR instruction path-length failed.

    The JTAG IR instruction scan-path is stuck-at-zero.

    The test for the JTAG DR bypass path-length failed.

    The JTAG DR bypass scan-path is stuck-at-zero.

    Muneeswaran manokaran said:

    Anybody know about this problem?

    Problem in my hardware or any-other setup?

    This is most commonly a HW connectivity issue. Please see:

    http://software-dl.ti.com/ccs/esd/documents/ccsv7_debugging_jtag_connectivity_issues.html#invalid-data-read-back

  • 0 in reply to Ki
    Intellectual 650 points
    Hi,
    Thanks. Problems is in my hardware setup to target board.(Ground mismatch).. But While debugging, I got above error(First posted).
    C55xx: GEL: Error while executing OnReset(0): Memory verification failed at address 0x80D

    at GEL_MemoryFill(0x80D, 2, 1, 0x4748) [c5502.gel:202]

    at Init_CE0_SDRAM_5502CPUBoard() [c5502.gel:66]

    at OnReset(0)

    C55xx: GEL Output: C5502_Init Complete.

    C55xx: GEL: Error while executing OnTargetConnect(): Memory verification failed at address 0x80D

    at GEL_MemoryFill(0x80D, 2, 1, 0x4748) [c5502.gel:202]

    at Init_CE0_SDRAM_5502CPUBoard() [c5502.gel:60]

    at OnTargetConnect()

    Also Code Composer Studio V8 is hanging while debug with target board.

    I am using Windows 10 -64 bit (CCS v8).
    Any suggestion?
  • 0 in reply to Muneeswaran manokaran
    Intellectual 650 points
    Hi,

    Now am using CCS v5.1. while debugging i got error

    C55xx: GEL Output: C5502_Init Complete.
    C55xx: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.
    C55xx: File Loader: Data verification failed at address 0x00FFFF00 Please verify target memory and memory map.
    C55xx: GEL: File: C:\Users\YEPL\workspace_v5_1\sample\Debug\sample.out: a data verification error occurred, file load failed.

    any solution?
    Thanks
    Muneeswaran Manokaran
  • 0 in reply to Muneeswaran manokaran
    TI__Guru**** 472211 points
    Data Verification Errors are a common error with many potential root causes. Please carefully read the below article for more details on the error, the potential root causes, and suggestions on how to resolve:
    software-dl.ti.com/.../ccs_troubleshooting.html

    Thanks
    ki
  • 0 in reply to Ki
    Intellectual 650 points
    Hi,
    Problem solved after GEL file changed.
    Thanks to all..