CCS/MSP432P401R: multichannel ADC

user5229881

Part Number: MSP432P401R

Tool/software: Code Composer Studio

i use AD1,AD16,AD17 to sample data,but resbuffer does not have number. I wonder what i do wrong?

    ADC14_enableModule();
    ADC14_initModule(ADC_CLOCKSOURCE_SMCLK, ADC_PREDIVIDER_1, ADC_DIVIDER_1, 0);


    /* Configuring GPIOs for Analog In */
    GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P5, GPIO_PIN7|GPIO_PIN6
            |GPIO_PIN4, GPIO_TERTIARY_MODULE_FUNCTION);
    GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P9,
            GPIO_PIN0 | GPIO_PIN1, GPIO_TERTIARY_MODULE_FUNCTION);

    /* Configuring ADC Memory (ADC_MEM1,16,17 with repeat)*/
        ADC14_configureMultiSequenceMode(ADC_MEM1, ADC_MEM17, true);
        ADC14_configureConversionMemory(ADC_MEM1,ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG,
                ADC_INPUT_A1, false);
        ADC14_configureConversionMemory(ADC_MEM16,ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG,
                ADC_INPUT_A16, false);
        ADC14_configureConversionMemory(ADC_MEM17,ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG,
                ADC_INPUT_A17, false);

        /* Enabling the interrupt when a conversion on channel 7 (end of sequence)
         *  is complete and enabling conversions */

        ADC14_enableInterrupt(ADC_INT17);
        /* Enabling Interrupts */
        Interrupt_enableInterrupt(INT_ADC14);
        Interrupt_enableMaster();

        /* Setting up the sample timer to automatically step through the sequence
         * convert.
         */
        ADC14_enableSampleTimer(ADC_AUTOMATIC_ITERATION);

        /* Triggering the start of the sample */
        ADC14_enableConversion();
        ADC14_toggleConversionTrigger();

        /*Set resolution*/
        ADC14_setResolution(ADC_14BIT);


void ADC14_IRQHandler(void)
{
    uint64_t status;

    status = MAP_ADC14_getEnabledInterruptStatus();
    MAP_ADC14_clearInterruptFlag(status);

    if(status & ADC_INT17)
    {
        MAP_ADC14_getMultiSequenceResult(resultsBuffer);
        ADC14_getResultArray(ADC_MEM1, ADC_MEM17,resultsBuffer);
    }
}

during ADC IRQ, ADC14_getResultArray(ADC_MEM1, ADC_MEM17,resultsBuffer) and

ADC14_getMultiSequenceResult(resultsBuffer) don't have any result

over 6 years ago

0 Chris Sterzik over 6 years ago

TI__Guru 70501 points

Hello. Here are some things to consider:

(1) You are using SMCLK as the ADC clock and the ADC sample timer to establish the sample and hold time. This means that the sample and hold time is 4 (default) SMCLK cycles. Please make sure this time is long enough. The sample capacitor is the multiplexed with the different channels, so if you do not provide enough time then you will simply measure the voltage on the sample capacitor which has not changed relative to the channel you are intending to measure.

(2) You are setting the resolution (ADC14_setResolution) after you have started conversions. The resolution can only be adjusted when ADC14ENC =0 (disabled). This api call will have no effect, but also the default is 14. The impact is '0' but this is not good practice.

(3) I would recommend changing the sequence to only use memory locations 0-2 with a mapping to channels 1, 16, and 17 respectively.

ADC14_configureMultiSequenceMode(ADC_MEM0, ADC_MEM2, true);
        ADC14_configureConversionMemory(ADC_MEM0,ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG,
                ADC_INPUT_A1, false);
        ADC14_configureConversionMemory(ADC_MEM1,ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG,
                ADC_INPUT_A16, false);
        ADC14_configureConversionMemory(ADC_MEM2,ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG,
                ADC_INPUT_A17, false);
...

        ADC14_enableInterrupt(ADC_INT2);

(4) Because you have selected a repeated auto scan- multiSequence is true and sampeTimer is AUTOMATIC_ITERATION, the timing needs to be considered when you are accessing the conversion results. For example channel A1 may be measured again after the interrupt but before the conversion results are read. If the three measurements need to be correlated in time, then you should use a different trigger or possibly the DMA to move the data in a ping-pong fashion.

Regards,
Chris

0 user5229881 over 6 years ago in reply to Chris Sterzik

Prodigy 235 points

thanks, where can i find the dma ping-pong mode to transfer multichannel ADC results?
and could i use timer a to trigger ADCs ,how can i configure it ?ASAP,thanks again

0 Chris Sterzik over 6 years ago in reply to user5229881

TI__Guru 70501 points

Fullscreen adc14_multiple_channel_repeat_timera_source_05a.c Download

/* --COPYRIGHT--,BSD_EX
 * Copyright (c) 2013, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * --/COPYRIGHT--
 */
//******************************************************************************
/*
 *
 * Timer (1MHz) Triggered sequence of conversions (ADC14 4,5,6), where each
 * conversion in the sequence is triggered manually and the sample-hold time
 * is a function of the negative duty cycle.
 * Timing of ADC14 in pulse-sample mode:
 *     Sample-hold: defined by timer 5 cycles (timer source is TACLK, 24Mhz)
 *     Sync: 2 cycle (25Mhz)
 *     Conversion: 16 cycles (25Mhz)
 *     Mem Transfer: 1 cycle (25Mhz)
 *
 * The ADC triggers the DMA which moves the data from ADCMEM to the array
 * memory.
 *
 */
#include <dma.h>
#include <ti/devices/msp432p4xx/driverlib/driverlib.h>
#include <stdio.h>

/* Standard Includes */
#include <stdint.h>
#include <string.h>

//#define WORKAROUND

/* Clock system frequencies */
#define MCLK_FREQUENCY      48000000
#define SMCLK_FREQUENCY     24000000

#define NUMBER_OF_SAMPLES       32
#define CONVERSIONS_PER_SAMPLE  3

#define ADC_TASKS               34

uint16_t dataSet_01[NUMBER_OF_SAMPLES][CONVERSIONS_PER_SAMPLE];
uint16_t dataSet_02[NUMBER_OF_SAMPLES][CONVERSIONS_PER_SAMPLE];

uint16_t sampleCnt;


/* DMA Control Table */
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(MSP_EXP432P401RLP_DMAControlTable, 1024)
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=1024
#elif defined(__GNUC__)
__attribute__ ((aligned (1024)))
#elif defined(__CC_ARM)
__align(1024)
#endif
static DMA_ControlTable MSP_EXP432P401RLP_DMAControlTable[16];  // 8 primary and 8 alternate

volatile uint8_t switch_data = 0;

const uint8_t forceP1B2ISR = 0x04;  // P1.2 is high
const uint8_t forceP1B3ISR = 0x09;  // P1.3 is high and P1.0 is high
/*
 * TA0 PWM Configuration
 * Timer used to Trigger ADC
 * SMCLK -> SMCLK_FREQUENCY
 * Sample Frequency -> SAMPLE_FREQUENCY
 */
const Timer_A_PWMConfig pwmConfig =
{
        TIMER_A_CLOCKSOURCE_SMCLK,              // 24Mhz
        TIMER_A_CLOCKSOURCE_DIVIDER_1,          //
//        23,                                     // 23+1 period,
        71,
        TIMER_A_CAPTURECOMPARE_REGISTER_1,      // Duty Cycle Defined in CCR1
        TIMER_A_OUTPUTMODE_SET_RESET,
        19                                      // Set on 19 and reset on 0
};

/* SPI Master Configuration Parameter */
const eUSCI_SPI_MasterConfig spiMasterConfig =
{
        EUSCI_B_SPI_CLOCKSOURCE_SMCLK,             // SMCLK Clock Source
        SMCLK_FREQUENCY,                           // SMCLK = DCO = 24MHZ
        12000000,                                  // SPICLK = 12Mhz
        EUSCI_B_SPI_MSB_FIRST,                     // MSB First
        EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT,    // Phase
        EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH, // High polarity
        EUSCI_B_SPI_3PIN                           // 3Wire SPI Mode
};
/* DMA Task Structure */
DMA_ControlTable pingTask,pongTask;
/*
 *
 */
const DMA_ControlTable AdcDmaSeq_01[ADC_TASKS] =
{
    /*
     * Task1,
     */
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[0][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
                /* Size=IncDest=IncSource=32
                 * srcEndAddr -> 0x400120A3
                 * dstEndAddr -> 0x2000000B
                 * control    -> 0xAA008027 : dst_inc=size=src_inc=size = word
                 *
                 * Size=IncDest=16 IncSource=32
                 * srcEndAddr -> 0x400120A3
                 * dstEndAddr -> 0x20000105
                 * control    -> 0x59008027 : dst_inc=size=halfword, src_inc = word, src_size = halfword
                 */
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[1][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
                /* Size=IncDest=IncSource=32
                 * srcEndAddr -> 0x400120A3
                 * dstEndAddr -> 0x20000017
                 * control    -> 0xAA008027
                 *
                 * Size=IncDest=16 IncSource=32
                 * srcEndAddr -> 0x400120A3
                 * dstEndAddr -> 0x2000010B
                 * control    -> 0x59008027
                 */
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[2][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[3][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[4][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[5][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[6][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[7][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[8][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[9][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[10][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[11][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[12][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[13][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[14][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[15][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[16][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[17][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[18][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[19][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[20][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[21][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[22][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[23][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[24][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[25][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[26][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[27][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[28][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[29][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[30][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_01[31][0],
                UDMA_ARB_4, UDMA_MODE_MEM_SCATTER_GATHER),

   DMA_TaskStructEntry(1, UDMA_SIZE_8,
                 UDMA_SRC_INC_8, (void *)&forceP1B2ISR,
                 UDMA_DST_INC_8, (void *)&P1->OUT,
                 UDMA_ARB_1, UDMA_MODE_MEM_SCATTER_GATHER),
    DMA_TaskStructEntry(4, UDMA_SIZE_32,
                UDMA_SRC_INC_32, (void *)&pongTask,
                UDMA_DST_INC_32, (void *)&MSP_EXP432P401RLP_DMAControlTable[7],
                UDMA_ARB_4, UDMA_MODE_MEM_SCATTER_GATHER)
};

const DMA_ControlTable AdcDmaSeq_02[ADC_TASKS] =
{
    /*
     * Task1,
     */
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[0][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[1][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[2][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[3][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[4][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[5][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[6][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[7][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[8][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[9][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[10][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[11][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[12][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[13][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[14][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[15][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[16][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[17][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[18][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[19][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[20][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[21][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[22][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[23][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[24][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[25][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[26][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[27][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[28][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[29][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[30][0],
                UDMA_ARB_4, UDMA_MODE_PER_SCATTER_GATHER),
    DMA_TaskStructEntry(3, UDMA_SIZE_16,
                UDMA_SRC_INC_32,(void*)&ADC14->MEM[0],
                UDMA_DST_INC_16, &dataSet_02[31][0],
                UDMA_ARB_4, UDMA_MODE_MEM_SCATTER_GATHER),

    DMA_TaskStructEntry(1, UDMA_SIZE_8,
                UDMA_SRC_INC_8, (void *)&forceP1B3ISR,
                UDMA_DST_INC_8, (void *)&P1->OUT,
                UDMA_ARB_1, UDMA_MODE_MEM_SCATTER_GATHER),
    DMA_TaskStructEntry(4, UDMA_SIZE_32,
                UDMA_SRC_INC_32, (void *)&pingTask,
                UDMA_DST_INC_32, (void *)&MSP_EXP432P401RLP_DMAControlTable[7],
                UDMA_ARB_4, UDMA_MODE_MEM_SCATTER_GATHER)
};

uint16_t adcIndex;
bool dataSet0Ready;

void sendData(uint16_t*);

int main(void)
{
    /* Halting WDT  */
    MAP_WDT_A_holdTimer();

    /*
     * Revision C silicon supports wait states of 1 at 48Mhz
     */
    MAP_PCM_setCoreVoltageLevel(PCM_VCORE1);
    MAP_FlashCtl_setWaitState(FLASH_BANK0, 1);
    MAP_FlashCtl_setWaitState(FLASH_BANK1, 1);

    /*
     * Setting up clocks
     * MCLK = MCLK = 48MHz
     * SMCLK = MCLK/2 = 24Mhz
     * ACLK = REFO = 32Khz
     */
    MAP_CS_setDCOFrequency(48000000);
    MAP_CS_initClockSignal(CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
    MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_2);
    MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);

    /*
     * Debug,
     * output TA0.1
     */
    P2->DIR |= (BIT4);
    P2->SEL0 |= BIT4;
    P2->SEL1 &= ~BIT4;

    /* Configuring P1.0 as output for debug */
    MAP_GPIO_setAsOutputPin(GPIO_PORT_P1, GPIO_PIN0);
    MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P1, GPIO_PIN0);

    /*
     * Non-conventional usage of P1.2 and P1.3 as 'internal' interrupt
     * triggered from DMA.
     */
    MAP_GPIO_setOutputLowOnPin(GPIO_PORT_P1, (GPIO_PIN2 + GPIO_PIN3));
    MAP_GPIO_setAsOutputPin(GPIO_PORT_P1, (GPIO_PIN2 + GPIO_PIN3));
    MAP_GPIO_interruptEdgeSelect(GPIO_PORT_P1,(GPIO_PIN2 + GPIO_PIN3),
                                    GPIO_LOW_TO_HIGH_TRANSITION);
    MAP_GPIO_clearInterruptFlag(GPIO_PORT_P1,(GPIO_PIN2 + GPIO_PIN3));
    MAP_GPIO_enableInterrupt(GPIO_PORT_P1,(GPIO_PIN2 + GPIO_PIN3));

    /* Selecting P1.5 P1.6 and P1.7 in SPI mode */
    MAP_GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P1,
            GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7, GPIO_PRIMARY_MODULE_FUNCTION);

    /* Configure P2.0, P2.1, and P2.2 for debug*/
    MAP_GPIO_setAsOutputPin(GPIO_PORT_P2, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2);
    MAP_GPIO_setOutputLowOnPin(GPIO_PORT_P2, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2);

    /* Configuring GPIOs for Analog In P4.5,4.6,4.7 */
    MAP_GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P4,
            GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7, GPIO_TERTIARY_MODULE_FUNCTION);

    /*
     * Initializing ADC (ADCOSC/1/1)
     * 25Mhz
     */
    MAP_ADC14_enableModule();
    MAP_ADC14_initModule(ADC_CLOCKSOURCE_ADCOSC, ADC_PREDIVIDER_1, ADC_DIVIDER_1,
            0);

    /* Configuring ADC Memory (ADC_MEM0 - ADC_MEM4 (A4 - A6)  with repeat)
     * with internal 2.5v reference */
    MAP_ADC14_configureMultiSequenceMode(ADC_MEM0, ADC_MEM2, true);
    MAP_ADC14_configureConversionMemory(ADC_MEM0,
            ADC_VREFPOS_AVCC_VREFNEG_VSS,
            ADC_INPUT_A4, ADC_NONDIFFERENTIAL_INPUTS);
    MAP_ADC14_configureConversionMemory(ADC_MEM1,
            ADC_VREFPOS_AVCC_VREFNEG_VSS,
            ADC_INPUT_A5, ADC_NONDIFFERENTIAL_INPUTS);
    MAP_ADC14_configureConversionMemory(ADC_MEM2,
            ADC_VREFPOS_AVCC_VREFNEG_VSS,
            ADC_INPUT_A6, ADC_NONDIFFERENTIAL_INPUTS);
    /*
     * Configuring the sample trigger to be sourced from Timer_A0 CCR1
     * and setting it to automatic iteration after it is triggered
     */
    MAP_ADC14_setSampleHoldTrigger(ADC_TRIGGER_SOURCE1, false);
    /*
     * Disable sample timer (default), use pulse mode.
     */
    MAP_ADC14_disableSampleTimer();
    MAP_ADC14_enableConversion();

    /* Configuring DMA module */
    MAP_DMA_enableModule();
    MAP_DMA_setControlBase(MSP_EXP432P401RLP_DMAControlTable);

     /* Disabling channel attributes */
    MAP_DMA_disableChannelAttribute(DMA_CH7_ADC14,
                                 UDMA_ATTR_USEBURST |
                                 UDMA_ATTR_HIGH_PRIORITY |
                                 UDMA_ATTR_REQMASK);

    MAP_DMA_setChannelScatterGather(DMA_CH7_ADC14,ADC_TASKS,(void*)&AdcDmaSeq_02[0],true);
    pongTask = MSP_EXP432P401RLP_DMAControlTable[7];

    MAP_DMA_setChannelScatterGather(DMA_CH7_ADC14,ADC_TASKS,(void*)&AdcDmaSeq_01[0],true);
    pingTask = MSP_EXP432P401RLP_DMAControlTable[7];

    MAP_DMA_assignChannel(DMA_CH7_ADC14);
    MAP_DMA_enableChannel(7);

    /*
     *
     */
    /* Configuring SPI in 3wire master mode */
    MAP_SPI_initMaster(EUSCI_B0_BASE, &spiMasterConfig);

    /* Enable SPI module */
    MAP_SPI_enableModule(EUSCI_B0_BASE);

    MAP_Interrupt_disableSleepOnIsrExit();

    MAP_Interrupt_enableInterrupt(INT_PORT1);
    MAP_Interrupt_enableMaster();

    /*
     * Starting the Timer
     * Configuring Timer_A in continuous mode and sourced from SMCLK
     */
    MAP_Timer_A_generatePWM(TIMER_A0_BASE, &pwmConfig);


    while(1)
    {
        MAP_PCM_gotoLPM0();
//        Debug
//        P2->OUT |= BIT0;
        if(dataSet0Ready)
        {
            /*
             *
             */
            sendData(&dataSet_01[0][0]);
        }
        else
        {
            sendData(&dataSet_02[0][0]);
        }
//        Debug
//        P2->OUT &= ~BIT0;
    }
}

#if     __TI_COMPILER_VERSION__ >= 15009000
__attribute__((ramfunc))
#endif
void sendData(uint16_t* arrayPtr)
{
    volatile uint16_t ii,jj;

    for(ii=0;ii<NUMBER_OF_SAMPLES;ii++)
    {
        for(jj=0;jj<CONVERSIONS_PER_SAMPLE;jj++)
        {
            while(!(EUSCI_B0->IFG & EUSCI_B_IFG_TXIFG0));
            EUSCI_B0->TXBUF = (uint8_t)arrayPtr[ii*3 + jj];
            while(!(EUSCI_B0->IFG & EUSCI_B_IFG_TXIFG0));
            EUSCI_B0->TXBUF = (uint8_t)(arrayPtr[ii*3 + jj]>>8);
        }
    }
}

#if     __TI_COMPILER_VERSION__ >= 15009000
__attribute__((ramfunc))
#endif
void PORT1_IRQHandler(void)
{
    uint32_t status;
    volatile uint16_t   ii;
//        Debug
//  P2->OUT |= BIT1;
    status = MAP_GPIO_getEnabledInterruptStatus(GPIO_PORT_P1);
    MAP_GPIO_clearInterruptFlag(GPIO_PORT_P1, status);

    if(status == GPIO_PIN2)
    {
        MAP_GPIO_setOutputLowOnPin(GPIO_PORT_P1, GPIO_PIN2);
        dataSet0Ready = true;
    }
    if(status == GPIO_PIN3)
    {
        MAP_GPIO_setOutputLowOnPin(GPIO_PORT_P1, GPIO_PIN3);
        dataSet0Ready = false;
    }
//        Debug
//    P2->OUT &= ~BIT1;
}

The DMA ping-pong mode is not really practical for multiple channel ADC results. I would recommend using the scatter-gather mode. Please find the attached example. It is a little dated, but should give you the information/structure needed.

Regards,

Chris

Code Composer Studio™︎

Code Composer Studio forum

CCS/MSP432P401R: multichannel ADC