CCS/TMS320F28069: Implementing XOR logic gate

Mohamed Salah

Part Number: TMS320F28069

Tool/software: Code Composer Studio

Dear Specialists,

I am trying to implement XOR logic gate for 3 inputs in a three-phase inverter system using Developmental Kit TMS320F28069.

I found that many people suggest ^ symbol to do this logic gate. But, unfortunately, the output is not as the expected one, since the the output to be HIGH, only one of the three inputs must be HIGH and the other two inputs must be LOW. If two inputs are HIGH, so the output of the XOR must be LOW.

In other words, only two inputs must be HIGH at any time.

The next figure describe the results that I got (NOT the desired one)

Channels 1 , 2 and 3 represent the inputs to the ^ XOR symbol utilized in the code

Channel 4 represents the output of the ^ XOR symbol.

What I want is If any two of the inputs are HIGH, then Channel 4 must be LOW.

if only one input is HIGH, the Channel 4 must be HIGH

The code is attached, What I want to check is at the end of the code.

I would be grateful if any one can help me to do this, since I can not complete my research work.

#include "DSP28x_Project.h"
#include <string.h>
#include <stdio.h>
#include <math.h>

// Code for DPWMMAX

extern Uint16 RamfuncsRunStart;
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadSize;
#pragma CODE_SECTION(EpwmsIsr, "ramfuncs");

interrupt void EpwmsIsr(void);
void EPwmsConfig();


static int count = 0;

int duty1;
int duty2;
int duty3;
int duty4;
int duty5;
int duty6;
int t_sys = 201;
static const double M_PI = 3.1415926535897932384626433832795;
static const double Mi = 0.8;

void main(void){

    DINT;
    InitSysCtrl();
    memcpy(&RamfuncsRunStart,&RamfuncsLoadStart,(Uint32)&RamfuncsLoadSize);
    InitFlash();
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;
    InitPieVectTable();

    EALLOW;
    PieVectTable.EPWM5_INT = EpwmsIsr;
    EDIS;

    EPwmsConfig();

    EINT;
    while(1){};
}

void EPwmsConfig(void){

    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;

    //GPIO Configuration
    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1;
    GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;

    //TB Module Configuration

    EPwm1Regs.TBCTL.bit.CLKDIV = 0;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
    EPwm1Regs.TBCTL.bit.CTRMODE = 2;
    EPwm1Regs.TBCTR = 0;
    EPwm1Regs.TBPRD = 4000;

    EPwm2Regs.TBCTL.bit.CLKDIV = 0;
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;
    EPwm2Regs.TBCTL.bit.CTRMODE = 2;
    EPwm2Regs.TBCTR = 0;
    EPwm2Regs.TBPRD = 4000;

    EPwm3Regs.TBCTL.bit.CLKDIV = 0;
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;
    EPwm3Regs.TBCTL.bit.CTRMODE = 2;
    EPwm3Regs.TBCTR = 0;
    EPwm3Regs.TBPRD = 4000;

    EPwm4Regs.TBCTL.bit.CLKDIV = 0;
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0;
    EPwm4Regs.TBCTL.bit.CTRMODE = 2;
    EPwm4Regs.TBCTR = 0;
    EPwm4Regs.TBPRD = 4000;

    EPwm5Regs.TBCTL.bit.CLKDIV = 0;
    EPwm5Regs.TBCTL.bit.HSPCLKDIV = 0;
    EPwm5Regs.TBCTL.bit.CTRMODE = 2;
    EPwm5Regs.TBCTR = 0;
    EPwm5Regs.TBPRD = 4000;

    EPwm6Regs.TBCTL.bit.CLKDIV = 0;
    EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0;
    EPwm6Regs.TBCTL.bit.CTRMODE = 2;
    EPwm6Regs.TBCTR = 0;
    EPwm6Regs.TBPRD = 4000;

    EPwm1Regs.CMPA.half.CMPA = 0;
    EPwm1Regs.CMPB = 1000;
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = 2;

    EPwm2Regs.CMPA.half.CMPA = 0;
    EPwm2Regs.CMPB = 1000;
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = 2;

    EPwm3Regs.CMPA.half.CMPA = 0;
    EPwm3Regs.CMPB = 1000;
    EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;
    EPwm3Regs.CMPCTL.bit.LOADAMODE = 2;

    EPwm4Regs.CMPA.half.CMPA = 0;
    EPwm4Regs.CMPB = 1000;
    EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0;
    EPwm4Regs.CMPCTL.bit.LOADAMODE = 2;

    EPwm5Regs.CMPA.half.CMPA = 0;
    EPwm5Regs.CMPB = 1000;
    EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0;
    EPwm5Regs.CMPCTL.bit.LOADAMODE = 2;

    EPwm6Regs.CMPA.half.CMPA = 0;
    EPwm6Regs.CMPB = 1000;
    EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;
    EPwm6Regs.CMPCTL.bit.LOADAMODE = 2;

    EPwm1Regs.AQCTLA.bit.CAU = 1;
    EPwm1Regs.AQCTLA.bit.CAD = 2;

    EPwm2Regs.AQCTLA.bit.CAU = 1;
    EPwm2Regs.AQCTLA.bit.CAD = 2;

    EPwm3Regs.AQCTLA.bit.CAU = 1;
    EPwm3Regs.AQCTLA.bit.CAD = 2;

    EPwm4Regs.AQCTLA.bit.CAU = 1;
    EPwm4Regs.AQCTLA.bit.CAD = 2;

    EPwm5Regs.AQCTLA.bit.CAU = 1;
    EPwm5Regs.AQCTLA.bit.CAD = 2;

    EPwm6Regs.AQCTLA.bit.CAU = 1;
    EPwm6Regs.AQCTLA.bit.CAD = 2;

    EPwm1Regs.DBCTL.bit.OUT_MODE = 3;
    EPwm1Regs.DBCTL.bit.POLSEL = 1;
    EPwm1Regs.DBCTL.bit.IN_MODE = 0;
    EPwm1Regs.DBCTL.bit.HALFCYCLE = 1;

    EPwm2Regs.DBCTL.bit.OUT_MODE = 3;
    EPwm2Regs.DBCTL.bit.POLSEL = 1;
    EPwm2Regs.DBCTL.bit.IN_MODE = 0;
    EPwm2Regs.DBCTL.bit.HALFCYCLE = 1;

    EPwm3Regs.DBCTL.bit.OUT_MODE = 3;
    EPwm3Regs.DBCTL.bit.POLSEL = 1;
    EPwm3Regs.DBCTL.bit.IN_MODE = 0;
    EPwm3Regs.DBCTL.bit.HALFCYCLE = 1;

    EPwm4Regs.DBCTL.bit.OUT_MODE = 3;
    EPwm4Regs.DBCTL.bit.POLSEL = 1;
    EPwm4Regs.DBCTL.bit.IN_MODE = 0;
    EPwm4Regs.DBCTL.bit.HALFCYCLE = 1;

    EPwm5Regs.DBCTL.bit.OUT_MODE = 3;
    EPwm5Regs.DBCTL.bit.POLSEL = 1;
    EPwm5Regs.DBCTL.bit.IN_MODE = 0;
    EPwm5Regs.DBCTL.bit.HALFCYCLE = 1;

    EPwm6Regs.DBCTL.bit.OUT_MODE = 3;
    EPwm6Regs.DBCTL.bit.POLSEL = 1;
    EPwm6Regs.DBCTL.bit.IN_MODE = 0;
    EPwm6Regs.DBCTL.bit.HALFCYCLE = 1;

    EPwm1Regs.DBRED = 180; //
    EPwm1Regs.DBFED = 180;

    EPwm2Regs.DBRED = 180; //
    EPwm2Regs.DBFED = 180;

    EPwm3Regs.DBRED = 180; //
    EPwm3Regs.DBFED = 180;

    EPwm4Regs.DBRED = 180; //
    EPwm4Regs.DBFED = 180;

    EPwm5Regs.DBRED = 180; //
    EPwm5Regs.DBFED = 180;

    EPwm6Regs.DBRED = 180;
    EPwm6Regs.DBFED = 180;

    //ET Module Configuration
    EPwm5Regs.ETSEL.bit.INTSEL = 3;
    EPwm5Regs.ETSEL.bit.INTEN = 1;
    EPwm5Regs.ETPS.bit.INTPRD = 1;
    EPwm5Regs.ETCLR.bit.INT = 1;

    //PIE Interrupt/CPU Interrupt Configuration
    PieCtrlRegs.PIEIER3.bit.INTx5 = 1;
    IER |= M_INT3;

    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;

    EDIS;
}

interrupt void EpwmsIsr(void){

    // Phase "A"
    if (count >= 0 && count < 67)
    {
        duty1 =(int) (2000+2000);
    }
    else if (count >= 67 && count < 201)
    {
        duty1 =(int) (2000-2*Mi*2000*sin((2*M_PI*count/(2*t_sys))-(M_PI/3))+2000);
    }
    else if (count >= 201 && count < 335)
    {
        duty1 =(int) (2000+2*Mi*2000*sin((2*M_PI*count/(2*t_sys))+(M_PI/3))+2000);
    }
    else
    {
        duty1 =(int) (2000+2000);
    }

    // Phase "B"
    if (count >= 0 && count < 67)
    {
        duty2 =(int) (2000+2*Mi*2000*sin((2*M_PI*count/(2*t_sys))-(M_PI/3))+2000);
    }
    else if (count >= 67 && count < 201)
    {
        duty2 =(int) (2000+2000);
    }
    else if (count >= 201 && count < 335)
    {
        duty2 =(int) (2000+2*Mi*2000*sin(2*M_PI*count/(2*t_sys))+2000);
    }
    else
    {
        duty2 =(int) (2000+2*Mi*2000*sin((2*M_PI*count/(2*t_sys))-(M_PI/3))+2000);
    }

    // Phase "C"
    if (count >= 0 && count < 67)
    {
        duty3 =(int) (2000-2*Mi*2000*sin((2*M_PI*count/(2*t_sys))+(M_PI/3))+2000);
    }
    else if (count >= 67 && count < 201)
    {
        duty3 =(int) (2000-2*Mi*2000*sin(2*M_PI*count/(2*t_sys))+2000);
    }
    else if (count >= 201 && count < 335)
    {
        duty3 =(int) (2000+2000);
    }
    else
    {
        duty3 =(int) (2000-2*Mi*2000*sin((2*M_PI*count/(2*t_sys))+(M_PI/3))+2000);
    }


    count = count + 1;
    if(count == 2*t_sys){
        count = 0;
    }
    EPwm1Regs.CMPA.half.CMPA = duty1;
    EPwm2Regs.CMPA.half.CMPA = duty2;
    EPwm3Regs.CMPA.half.CMPA = duty3;



    // what I want to program is the next line
    EPwm4Regs.CMPA.half.CMPA = EPwm1Regs.CMPA.half.CMPA ^ EPwm2Regs.CMPA.half.CMPA ^ EPwm3Regs.CMPA.half.CMPA;




    EPwm5Regs.ETCLR.bit.INT = 1;

    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

Thanks in advance

over 6 years ago

0 Mohamed Salah over 6 years ago

Prodigy 60 points

This is the desired output from the XOR logic gate. I would be grateful if any one can help me to obtain this output.

0 Nima Eskandari over 6 years ago in reply to Mohamed Salah

TI__Guru 52040 points

XOR in C is ^

So to implement three input XOR, you can do:

A_XOR_B = A^B

A_XOR_B_XOR_C = A_XOR_B ^ C

Nima

0 Keith Barkley over 6 years ago in reply to Mohamed Salah

Guru 42085 points

The problem is that a more-than-two input xor is ambiguous.

It would be best to do what you have to do to get your truth table implemented.

Have you tried a Karnaugh Map?

en.wikipedia.org/.../Karnaugh_map

0 Mohamed Salah over 6 years ago in reply to Nima Eskandari

Prodigy 60 points

Dear Mr. Nima Eskandari,

Thank you for you reply about dividing the process into 2 stages. I already tried this method, but unfortunately the output is always HIGH.

0 Mohamed Salah over 6 years ago in reply to Keith Barkley

Prodigy 60 points

Dear Mr. Keith Barkley,

Thank you for your reply. I tried to use IF statement to implement such logic gate by dividing the 3 inputs into 2 stages, but also the output is always HIGH.

0 Mohamed Salah over 6 years ago in reply to Mohamed Salah

Prodigy 60 points

Dear respected TI community members,

Due the unknown data type (at least for me) of the registers. Finally, I have to use the analog approach implementation instead of the digital approach. Therefore, I used the TC4030 Quad Exclusive-OR Gate IC.

This IC gives me the desired output by utilizing two XOR gates with two inputs each.

thank you for your kind attention and consideration.

Best Regards.

Code Composer Studio™︎

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CCS/TMS320F28069: Implementing XOR logic gate