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CCS/TMS320C6748: C6748 memory map in linker cmd file

Part Number: TMS320C6748
Other Parts Discussed in Thread: OMAPL138, SYSBIOS

Tool/software: Code Composer Studio

I have a C6748 custom board. We have a USB logging feature (in msc host mode) via USB OTG interface.

Everything runs well in simulation run using jtag but it crashes with flashed target.

I have noticed the memory map in the cmd file does something with my problem.

--args=64
MEMORY
{
      FLASH_CS2     org=0x60000000 len=0x02000000 /* AEMIF CS2 region */
      FLASH_BOOT    org=0x62000000 len=0x02000000 /* AEMIF CS3 region */
      FLASH_CS4     org=0x64000000 len=0x02000000 /* AEMIF CS4 region */
      SHRAM         org=0x66000000 len=0x02000000
}

SECTIONS
{

    .aemif_mem :
    {   
    } > FLASH_BOOT, RUN_START(NANDStart)

    "CFG" > DDR_CFG

    "DDR" > DDR

    .bss        > SHRAM  <--------------- this makes difference
    .text       > DDR  
    .stack      > DDR                            
    .cio        > DDR                            
    .const      > DDR                            
    .data       > DDR                            
    .switch     > DDR                            
    .sysmem     > DDR                            
    .far        > DDR                        
    .args       > DDR

    /* COFF sections */
    .pinit      > DDR
    .cinit      > DDR

    .ddrram  :
    {   
        . += 0x07000000;
    } > DDR, type=DSECT, RUN_START(EXTERNAL_RAM_START), RUN_END(EXTERNAL_RAM_END)

}

** If i remove .bss macro from the SECTION, then at least it doesn't crash in the flashed target but USB logging not working in simulation

If I add .bass to the SECTION, then USB logging works in simulation, but it crashes in flashed target.

What did I do wrong??

Thanks,

Dan

  • Here's my actual memory map.

    -stack 0x2000
    -heap 0x1000

    --args=64
    MEMORY
    {     
          FLASH_CS2     org=0x60000000 len=0x02000000 /* AEMIF CS2 region */
          FLASH_BOOT    org=0x62000000 len=0x02000000 /* AEMIF CS3 region */
          FLASH_CS4     org=0x64000000 len=0x02000000 /* AEMIF CS4 region */
    }

    SECTIONS
    {

        .aemif_mem :
        {   
        } > FLASH_BOOT, RUN_START(NANDStart)

        "CFG" > DDR_CFG

        "DDR" > DDR

        .bss        > DDR
        .text       > DDR  
        .stack      > DDR                            
        .cio        > DDR                            
        .const      > DDR                            
        .data       > DDR                            
        .switch     > DDR                            
        .sysmem     > DDR                            
        .far        > DDR                        
        .args       > DDR

        /* COFF sections */
        .pinit      > DDR
        .cinit      > DDR

        .ddrram  :
        {   
            . += 0x04000000;
        } > DDR, type=DSECT, RUN_START(EXTERNAL_RAM_START), RUN_END(EXTERNAL_RAM_END)

    }

  • Which Processor SDK RTOS is this?

    Best Regards,
    Yordan

  • It's a TMS320C6748 based custom board with an external DDR 128 MB.

    It always crashes at flash boot when USB_open gets hit. But, it runs fine in jtag simulation mode. This is a part of Usb logging feature in host mode in our product.

    if I remove USB_open() from the code, then no crashes in flash booting.

  • pdk_omapl138_1_0_8 is used.

    Compiler TI V8.3.3

    XDC 3.51.1.18_core

    SYSBIOS 6.75.2.00

    CUSTOM PLATFORM:

    metaonly module Platform inherits xdc.platform.IPlatform {

        config ti.platforms.generic.Platform.Instance CPU =
            ti.platforms.generic.Platform.create("CPU", {
                clockRate:      300.0,
                catalogName:    "ti.catalog.c6000",
                deviceName:     "TMS320C6748",
                customMemoryMap:
               [
                    ["IRAM",
                         {
                            name: "IRAM",
                            base: 0x11800000,
                            len: 0x00040000,
                            space: "code/data",
                            access: "RWX",
                         }
                    ],
                    ["IROM",
                         {
                            name: "IROM",
                            base: 0x11700000,    
                            len: 0x00100000,    
                            space: "code/data",
                            access: "RX",
                         }
                    ],
                    ["L3_CBA_RAM",
                         {
                            name: "L3_CBA_RAM",
                            base: 0x80000000,    
                            len: 0x00020000,    
                            space: "code/data",
                            access: "RWX",
                         }
                    ],
                    ["DDR",
                         {
                            name: "DDR",
                            base: 0xC0000000,    
                            len: 0x7FF33EC,    
                            space: "code/data",
                            access: "RWX",
                         } ],
                    ["DDR_CFG",
                         {
                            name: "DDR_CFG",
                            base: 0xC7FF33EC,
                            len: 0xCC14,
                            space: "code/data",
                            access: "RWX",
                         }
                    ],
               ],
              l2Mode: "0k",
              l1PMode: "32k",
              l1DMode: "32k",

        });

    instance :

        override config string codeMemory  = "DDR";
        override config string dataMemory  = "DDR";
        override config string stackMemory = "IRAM";

        config String l2Mode = "0k";
        config String l1PMode = "32k";
        config String l1DMode = "32k";
    }

    CUSTOM

                    ],

  • The size of our .out file is approx 4.7MB.

  • Hi Daniel,

    This sounds like something was not configured properly in AISgen (i.e. PSC or PINMUX not configured for USB) so the bootloader is not initializing something that was previously initialized in the GEL file. 

    After your device fails to boot, I recommend running the Debug GEL file as described in section 4 of the OMAPL138/C6748 ROM Bootloader Resources and FAQ application note to determine the state of the PSC and PLLs. You can share the output here. Please share which GEL file you are using and your AISgen settings as well.

  • Hi, pinmuxing is done as a part of usb initialization in the main().

    void Init_USB(void)
    {
        Uint16 i;

        // BOARD UNLOCK
        sysRegs->KICK0R = 0x83e70b13; // Write Access Key 0
        sysRegs->KICK1R = 0x95A4F1E0; // Write Access Key 1

        // C6748 PINMUXING for USB
        sysRegs->PINMUX9 |= (0x1 << 4); // Set bit4 Pinmux9 for USB Use
        sysRegs->PINMUX9&= 0xFFFFFF7F;  // Clear bit 7 Pinmux9 for USB Use

        // Reset the USB controller:
        usbRegs->CTRLR|= 0x00000001;

        // Wait until controller is finished with Reset.
        // When done, it will clear the RESET bit field.
        while((usbRegs->CTRLR& 0x1) == 1);

        // RESET: Hold PHY in Reset
        sysRegs->CFGCHIP2 |= 0x00008000; // Hold PHY in Reset

        // Drive Reset for few clock cycles
        for (i=0;i<50; i++); sysRegs->CFGCHIP2&= 0xFFFF7FFF;// Release PHY from Reset

        //Configure PHY with the Desired Operation

        // OTGMODE
        sysRegs->CFGCHIP2&= 0xFFFF9FFF;// 00=> Do Not OverridePHY Values

        // PHYPWDN
        sysRegs->CFGCHIP2&= 0xFFFFFBFF;// 1/0 => PowerdDown/NormalOperation

        // OTGPWRDN
        sysRegs->CFGCHIP2&= 0xFFFFFDFF;// 1/0 => PowerDown/NormalOperation

        // DATAPOL
        sysRegs->CFGCHIP2|= 0x00000100;// 1/0 => Normal/Reversed

        // SESNDEN
        sysRegs->CFGCHIP2|= 0x00000020;// 1/0 => NormalOperation/SessionEnd

        // VBDTCTEN
        sysRegs->CFGCHIP2|= 0x00000010;// 1/0 => VBUS Comparator Enable/Disable

        // Configure PHY PLL use and Select Source

        // REF_FREQ[3:0]
        sysRegs->CFGCHIP2|= 0x00000002;// 0010b=> 24MHzInputSource
    ...

    ...

    ...

    GEL: I am using C6748_LCDK.gel file without any modification. Should I modify the GEL file?

    AISgen:

    [ GENERAL TAB]

    device type: d800k008 DSP

    boot mode: NAND Flash

    Clock Source : Crystal at 24Mhz

    Check-box checked: Configure PLL0, Configure PSC, Configure DDR

  • Hi Daniel,

    If your application is running fine using the LCDK GEL file without modification then you should be okay. And if you are doing pinmuxing in your application then we can rule that out. 

    After your device boots, could you please run the attached debug GEL file and share the output here?

    OMAPL1x_debug_v9.zip

    OMAPL1x_debug_v9_CCSv6.zip

  • Will try your gel files.

    Not sure if this might be helpful for debugging but i see the below when "--mem_model:const=data --mem_model:data=far" options added to compile:

    Description    Resource    Path    Location    Type
    <a href="processors.wiki.ti.com/.../17003"> QueueDescriptor.c: relocation from function "ti_uia_runtime_QueueDescriptor_addToList__E" to symbol "ti_uia_runtime_QueueDescriptor_gPtrToFirstDescriptor" overflowed; the 21-bit relocated address 0x115d5c is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\uia_2_30_01_02\packages\ti\uia\runtime\lib\release\ti.uia.runtime.ae674<QueueDescriptor.oe674>", offset = 0x0000005c, section = ".text:ti_uia_runtime_QueueDescriptor_addToList__E")    PDI_Razor        line 111    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> QueueDescriptor.c: relocation from function "ti_uia_runtime_QueueDescriptor_addToList__E" to symbol "ti_uia_runtime_QueueDescriptor_gPtrToFirstDescriptor" overflowed; the 21-bit relocated address 0x115d5c is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\uia_2_30_01_02\packages\ti\uia\runtime\lib\release\ti.uia.runtime.ae674<QueueDescriptor.oe674>", offset = 0x0000006c, section = ".text:ti_uia_runtime_QueueDescriptor_addToList__E")    PDI_Razor        line 112    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> QueueDescriptor.c: relocation from function "ti_uia_runtime_QueueDescriptor_addToList__E" to symbol "ti_uia_runtime_QueueDescriptor_gUpdateCount" overflowed; the 21-bit relocated address 0x115d5d is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\uia_2_30_01_02\packages\ti\uia\runtime\lib\release\ti.uia.runtime.ae674<QueueDescriptor.oe674>", offset = 0x000000bc, section = ".text:ti_uia_runtime_QueueDescriptor_addToList__E")    PDI_Razor        line 135    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> QueueDescriptor.c: relocation from function "ti_uia_runtime_QueueDescriptor_addToList__E" to symbol "ti_uia_runtime_QueueDescriptor_gUpdateCount" overflowed; the 21-bit relocated address 0x115d5d is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\uia_2_30_01_02\packages\ti\uia\runtime\lib\release\ti.uia.runtime.ae674<QueueDescriptor.oe674>", offset = 0x000000d0, section = ".text:ti_uia_runtime_QueueDescriptor_addToList__E")    PDI_Razor        line 135    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/FATFS_drv.c: relocation from function "FATFS_close" to symbol "FATFS_volumeStatus$0" overflowed; the 21-bit relocated address 0x115d5b is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\fs\fatfs\lib\c674\release\ti.fs.fatfs.ae674<FATFS_drv.oe674>", offset = 0x00000120, section = ".text:FATFS_close")    PDI_Razor        line 149    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/FATFS_drv.c: relocation from function "FATFS_diskInitialize" to symbol "FATFS_volumeStatus$0" overflowed; the 21-bit relocated address 0x115d5b is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\fs\fatfs\lib\c674\release\ti.fs.fatfs.ae674<FATFS_drv.oe674>", offset = 0x000000ec, section = ".text:FATFS_diskInitialize$0")    PDI_Razor        line 425    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/FATFS_drv.c: relocation from function "FATFS_init" to symbol "FATFS_count$0" overflowed; the 21-bit relocated address 0x115d5a is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\fs\fatfs\lib\c674\release\ti.fs.fatfs.ae674<FATFS_drv.oe674>", offset = 0x00000000, section = ".text:FATFS_init")    PDI_Razor        line 191    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/FATFS_drv.c: relocation from function "FATFS_init" to symbol "FATFS_count$0" overflowed; the 21-bit relocated address 0x115d5a is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\fs\fatfs\lib\c674\release\ti.fs.fatfs.ae674<FATFS_drv.oe674>", offset = 0x0000002c, section = ".text:FATFS_init")    PDI_Razor        line 201    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/FATFS_drv.c: relocation from function "FATFS_init" to symbol "FATFS_count$0" overflowed; the 21-bit relocated address 0x115d5a is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\fs\fatfs\lib\c674\release\ti.fs.fatfs.ae674<FATFS_drv.oe674>", offset = 0x00000084, section = ".text:FATFS_init")    PDI_Razor        line 201    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/FATFS_drv.c: relocation from function "FATFS_open" to symbol "FATFS_volumeStatus$0" overflowed; the 21-bit relocated address 0x115d5b is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\fs\fatfs\lib\c674\release\ti.fs.fatfs.ae674<FATFS_drv.oe674>", offset = 0x0000034c, section = ".text:FATFS_open")    PDI_Razor        line 149    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/FATFS_drv.c: relocation from function "FATFS_open" to symbol "FATFS_volumeStatus$0" overflowed; the 21-bit relocated address 0x115d5b is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\fs\fatfs\lib\c674\release\ti.fs.fatfs.ae674<FATFS_drv.oe674>", offset = 0x0000035c, section = ".text:FATFS_open")    PDI_Razor        line 312    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/tirtos/HwiP_tirtos.c: relocation from function "HwiP_create" to symbol "gOsalHwiAllocCnt" overflowed; the 21-bit relocated address 0x115d50 is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\osal\lib\tirtos\omapl138\c674\release\ti.osal.ae674<HwiP_tirtos.oe674>", offset = 0x0000006c, section = ".text:HwiP_create")    PDI_Razor        line 152    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/tirtos/HwiP_tirtos.c: relocation from function "HwiP_create" to symbol "gOsalHwiAllocCnt" overflowed; the 21-bit relocated address 0x115d50 is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\osal\lib\tirtos\omapl138\c674\release\ti.osal.ae674<HwiP_tirtos.oe674>", offset = 0x000000c4, section = ".text:HwiP_create")    PDI_Razor        line 158    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/tirtos/HwiP_tirtos.c: relocation from function "HwiP_create" to symbol "gOsalHwiPeak" overflowed; the 21-bit relocated address 0x115d51 is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\osal\lib\tirtos\omapl138\c674\release\ti.osal.ae674<HwiP_tirtos.oe674>", offset = 0x00000060, section = ".text:HwiP_create")    PDI_Razor        line 152    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/tirtos/HwiP_tirtos.c: relocation from function "HwiP_create" to symbol "gOsalHwiPeak" overflowed; the 21-bit relocated address 0x115d51 is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\osal\lib\tirtos\omapl138\c674\release\ti.osal.ae674<HwiP_tirtos.oe674>", offset = 0x000000cc, section = ".text:HwiP_create")    PDI_Razor        line 152    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/tirtos/SemaphoreP_tirtos.c: relocation from function "SemaphoreP_create" to symbol "gOsalSemAllocCnt" overflowed; the 21-bit relocated address 0x115d4c is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\osal\lib\tirtos\omapl138\c674\release\ti.osal.ae674<SemaphoreP_tirtos.oe674>", offset = 0x00000074, section = ".text:SemaphoreP_create")    PDI_Razor        line 108    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/tirtos/SemaphoreP_tirtos.c: relocation from function "SemaphoreP_create" to symbol "gOsalSemAllocCnt" overflowed; the 21-bit relocated address 0x115d4c is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\osal\lib\tirtos\omapl138\c674\release\ti.osal.ae674<SemaphoreP_tirtos.oe674>", offset = 0x00000104, section = ".text:SemaphoreP_create")    PDI_Razor        line 119    C/C++ Problem
    <a href="processors.wiki.ti.com/.../17003"> src/tirtos/SemaphoreP_tirtos.c: relocation from function "SemaphoreP_create" to symbol "gOsalSemPeak" overflowed; the 21-bit relocated address 0x115d4d is too large to encode in the 15-bit unsigned field (type = 'R_C6000_SBR_U15_W' (13), file = "G:\ti\win\pdk_omapl138_1_0_8\packages\ti\osal\lib\tirtos\omapl138\c674\release\ti.osal.ae674<SemaphoreP_tirtos.oe674>", offset = 0x00000040, section = ".text:SemaphoreP_create")    PDI_Razor        line 113    C/C++ Problem

    **BUT**, Flash boot works fine with USB not working. If I select "--mem_model:const=data --mem_model:data=far_aggregates", then no warning messages but flash boot crashes.

  • C674X_0: GEL Output:
    ---------------------------------------------
    C674X_0: GEL Output: |             Device Information            |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
    C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_02 = 0x00000010
    C674X_0: GEL Output: DEV_INFO_03 = 0x00000005
    C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
    C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
    C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-4519626-7-37-17
    C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 5,0,0,6795
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
    C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
    C674X_0: GEL Output: DEV_INFO_21 = 0x3830306B
    C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_24 = 0x07011025
    C674X_0: GEL Output: DEV_INFO_25 = 0x0044F6CA
    C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
    C674X_0: GEL Output: DEV_INFO_26 = 0x35160005
    C674X_0: GEL Output:

    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: |               BOOTROM Info                |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: ROM ID: d800k008
    C674X_0: GEL Output: Silicon Revision 2.1
    C674X_0: GEL Output: Boot pins: 16
    C674X_0: GEL Output: Boot Mode: NAND 16
    C674X_0: GEL Output:
    ROM Status Code: 0x00000000
    Description:C674X_0: GEL Output: No error
    C674X_0: GEL Output:
    Program Counter (PC) = 0xC0C9CA04
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: |              Clock Information             |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: PLLs configured to utilize crystal.
    C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
    C674X_0: GEL Output:
    C674X_0: GEL Output: NOTE:  All clock frequencies in following PLL sections are based
    C674X_0: GEL Output: off OSCIN = 24 MHz.  If that value does not match your hardware
    C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
    C674X_0: GEL Output: and then reload.
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: |              PLL0 Information             |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: PLL0_SYSCLK1 = 300 MHz
    C674X_0: GEL Output: PLL0_SYSCLK2 = 150 MHz
    C674X_0: GEL Output: PLL0_SYSCLK3 = 25 MHz
    C674X_0: GEL Output: PLL0_SYSCLK4 = 75 MHz
    C674X_0: GEL Output: PLL0_SYSCLK5 = 100 MHz
    C674X_0: GEL Output: PLL0_SYSCLK6 = 300 MHz
    C674X_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: |              PLL1 Information             |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
    C674X_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
    C674X_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: |              PSC0 Information             |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: State Decoder:
    C674X_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
    C674X_0: GEL Output:  1 = SyncReset (reset assered, clock on)
    C674X_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
    C674X_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
    C674X_0: GEL Output: >3 = Transition in progress
    C674X_0: GEL Output:
    C674X_0: GEL Output: Module 0:    EDMA3CC (0)        STATE = 3
    C674X_0: GEL Output: Module 1:    EDMA3 TC0          STATE = 3
    C674X_0: GEL Output: Module 2:    EDMA3 TC1          STATE = 3
    C674X_0: GEL Output: Module 3:    EMIFA (BR7)        STATE = 3
    C674X_0: GEL Output: Module 4:    SPI 0              STATE = 3
    C674X_0: GEL Output: Module 5:    MMC/SD 0           STATE = 3
    C674X_0: GEL Output: Module 6:    AINTC              STATE = 0
    C674X_0: GEL Output: Module 7:    ARM RAM/ROM        STATE = 3
    C674X_0: GEL Output: Module 9:    UART 0             STATE = 3
    C674X_0: GEL Output: Module 10:    SCR 0 (BR0/1/2/8)  STATE = 3
    C674X_0: GEL Output: Module 11:    SCR 1 (BR4)        STATE = 3
    C674X_0: GEL Output: Module 12:    SCR 2 (BR3/5/6)    STATE = 3
    C674X_0: GEL Output: Module 13:    PRUSS              STATE = 0
    C674X_0: GEL Output: Module 14:    ARM                STATE = 0
    C674X_0: GEL Output: Module 15:    DSP                STATE = 3
    C674X_0: GEL Output:
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: |              PSC1 Information             |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output:
    C674X_0: GEL Output: State Decoder:
    C674X_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
    C674X_0: GEL Output:  1 = SyncReset (reset assered, clock on)
    C674X_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
    C674X_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
    C674X_0: GEL Output: >3 = Transition in progress
    C674X_0: GEL Output:
    C674X_0: GEL Output: Module 0:    EDMA3CC (1)        STATE = 3
    C674X_0: GEL Output: Module 1:    USB0 (2.0)         STATE = 3
    C674X_0: GEL Output: Module 2:    USB1 (1.1)         STATE = 3
    C674X_0: GEL Output: Module 3:    GPIO               STATE = 3
    C674X_0: GEL Output: Module 4:    UHPI               STATE = 3
    C674X_0: GEL Output: Module 5:    EMAC               STATE = 3
    C674X_0: GEL Output: Module 6:    DDR2 and SCR F3    STATE = 3
    C674X_0: GEL Output: Module 7:    MCASP0 + FIFO      STATE = 3
    C674X_0: GEL Output: Module 8:    SATA               STATE = 3
    C674X_0: GEL Output: Module 9:    VPIF               STATE = 3
    C674X_0: GEL Output: Module 10:    SPI 1              STATE = 3
    C674X_0: GEL Output: Module 11:    I2C 1              STATE = 3
    C674X_0: GEL Output: Module 12:    UART 1             STATE = 3
    C674X_0: GEL Output: Module 13:    UART 2             STATE = 3
    C674X_0: GEL Output: Module 14:    MCBSP0 + FIFO      STATE = 3
    C674X_0: GEL Output: Module 15:    MCBSP1 + FIFO      STATE = 3
    C674X_0: GEL Output: Module 16:    LCDC               STATE = 3
    C674X_0: GEL Output: Module 17:    eHRPWM (all)       STATE = 3
    C674X_0: GEL Output: Module 18:    MMC/SD 1           STATE = 3
    C674X_0: GEL Output: Module 19:    UPP                STATE = 3
    C674X_0: GEL Output: Module 20:    eCAP (all)         STATE = 3
    C674X_0: GEL Output: Module 21:    EDMA3 TC2          STATE = 3
    C674X_0: GEL Output: Module 24:    SCR-F0 Br-F0       STATE = 3
    C674X_0: GEL Output: Module 25:    SCR-F1 Br-F1       STATE = 3
    C674X_0: GEL Output: Module 26:    SCR-F2 Br-F2       STATE = 3
    C674X_0: GEL Output: Module 27:    SCR-F6 Br-F3       STATE = 3
    C674X_0: GEL Output: Module 28:    SCR-F7 Br-F4       STATE = 3
    C674X_0: GEL Output: Module 29:    SCR-F8 Br-F5       STATE = 3
    C674X_0: GEL Output: Module 30:    Br-F7 (DDR Contr)  STATE = 3
    C674X_0: GEL Output: Module 31:    L3 RAM, SCR-F4, Br-F6 STATE = 3

  • Hi Daniel,

    Thanks for the update. We will look into this and get back to you.

    In the meantime, could you please see if this AISgen config file for the LCDK works for you?

    LCDK_AISGen_Config.cfg

    Also, could you please confirm that you ran the debug GEL file after booting the device using the bootloader (and not CCS)?

    Regards,
    Sahin

  • Daniel,

    Can you please indicate where you obtained the linker command file. The SHRAM or the onchip RAM on this devices is located at 0x80000000 and not at 0x66000000 which is address reserved for direct addressing of the EMIFA CS5 asynchronous memory interface. Does your design use SDRAM connected to EMIFA ?  Can you also indicate if the application is directly being booted from ROM or is it a two stage boot using secondary bootloader(SBL)

    Note that the Initialization done when booting from NAND and debugging using GEL files is different. When debugging the GEL setup up the clocks and DDR and PSC on the device and puts the core in a clean state. In the ROM boot scenerio, the AIS config of your boot image and the boot media guides the ROM code to initialize the device clockc,pinmux, PSC and memory interfaces. YOu can run the debug GEL script in the JTAG working setup and when the application fails and compare the system state in the two setups. Note that when debugging the boot scenario remove any other GELs other than the debug GEL to prevent conflicts.

    Boot debugging tricks are described here:

    http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_Foundational_Components.html#software-debug-steps

    One additional experiment that may be useful would be to check if relocating the .bss to onchip SHRAM makes your application functional. Also, Please describe if the USB module is externally clocked. 

    Regards,

    Rahul

  • I actually suspect TI's USB driver.

    extern const USB_Config USB_config[];

    USB_Handle open_USB(unsigned int index, USB_Params *params)
    {
        USB_Handle         handle;
        handle = (USB_Handle)&(USB_config[index]);

        return (handle->fxnTablePtr->openFxn(handle, params)); <------------ CRASHES HERE DURING BOOT FROM FLASH.
    }

  • Daniel,

    Thanks for root causing this to specific region in code where the code seems to fail. you can set a break point at USB_open_musb in the file located at pdk_omapl138_1_0_xx\packages\ti\drv\usb\src\musb to narrow this down further. It will eventually call either  of the following functions that expect the USB clocks to be supplied 

    • static void setupMusbDevMsc(USB_Params* params);
    • static void setupMusbHostMsc(USB_Params* params);
    • static void setupMusbDevAc(USB_Params* params);

    USB2.0 on this device is clocked using SYSCLK2 and USB1.1 is clocked using external clock. Is there any configuration of this clock in the AISGen that may be different from how it is setup in the GEL files.

    Regards,

    Rahul