Tool/software: Code Composer Studio
Hi experts.
I will have to develop a big test application for our client using this EVM board (in future a custom board based on K2H processor will be used).
I'd like to use DSP CORE0 for test all DDR3B memory (2GB); for DDR3A I want to use ARM0 core (UBOOT modified to test only DDR3A memory bank).
Now I have removed the SODIM module from EVM board (to assured to use only DDR3B bank), but I don't kown how access at all 2GB memory.
I have tried to use MPAX register (with any success).
I use ti-processor-sdk-rtos-k2hk-evm-05.02.00.10-Linux-x86-Install.bin (for DSP core) and ti-processor-sdk-linux-k2hk-evm-05.02.00.10-Linux-x86-Install.bin (for ARM core). The application runs on only CORE0 with bios-tirtos. I have defined an Platform via "RTSC tool" menu defined (both the buses) mapped at 0x9_0000_0000 (len=0x8000_0000: 2GBytes) for DDR3A and 0x8_8000_0000 (len=0x8000_0000: 2GBytes).
I have insert the following line in cfg file:
Program.sectMap[".ddr3BMemSect"] = "DDR3B";
And I have insert the following C code:
#define DRAM_SIZE (0x8000000/sizeof(uint64_t)) // DDR size in 64 bit word
#pragma DATA_SECTION(ddr3BMem, ".ddr3BMemSect")
volatile uint64_t ddr3BMem[DRAM_SIZE/32];
// for another problem now I use only a part of the first ddr3B block memory, I think it's a my bug but the debuger hang the target
#define DDR_WRITE(addr, value) \
{ uint64_t offset = ((uint64_t)addr)&0xFFFFFFFF; \
ddr3BMem[offset] = value; \
}
#define DDR_READ(addr, value) \
{ uint64_t offset = ((uint64_t)addr)&0xFFFFFFFF; \
*value = ddr3BMem[offset]; \
}
#define XMC_BASE_ADDR (0x08000000)
#define XMPAX4_L (*(volatile unsigned int*)(XMC_BASE_ADDR + 0x00000020))
#define XMPAX4_H (*(volatile unsigned int*)(XMC_BASE_ADDR + 0x00000024))
void myxmc_setup(void) // my function to map DDR3B memory using MPAX[4] remapped in 0x9_0000_0000
{
int i;
static int tmp = 0;
if (tmp != 1)
{
tmp = 1;
CSL_BootCfgUnlockKicker();
XMPAX4_L = 0x900000BF; //9:0000_0000
XMPAX4_H = 0x0000001E; // 0000_0000 + seg size="1E" 2G
for (i = 0; i < 1000; i++)
platform_delay(10);
if (DDR3Init() != CSL_SOK)
{
platform_errno = PLATFORM_ERRNO_GENERIC;
CSL_BootCfgLockKicker();
return;
}
CSL_BootCfgLockKicker();
}
}
CSL_Status DDR3Init()
{
CSL_Status status = CSL_SOK;
//CSL_BootCfgUnlockKicker(); //removed from here
init_ddrphy(TCI6638_DDR3B_DDRPHYC, &ddr3phy_1600_64);
init_ddremif(TCI6638_DDR3B_EMIF_CTRL_BASE, &ddr3_1600_64);
return (status);
}
void EVM_init(void)
{
/* Status of the call to initialize the platform */
Int32 pform_status;
platform_init_flags init_flags;
platform_init_config init_config;
/* Set default values */
/*
* You can choose what to initialize on the platform by setting the following
* flags. We will initialize everything.
*/
memset(&init_flags, 0x00, sizeof(platform_init_flags));
memset(&init_config, 0x00, sizeof(platform_init_config));
init_flags.pll = 1; // PLLs for clocking
init_flags.ddr = 1; // External memory
init_flags.tcsl = 1; // Time stamp counter
init_flags.ecc = 0; // Memory ECC// I kept ECC disabled :
pform_status = platform_init(&init_flags, &init_config);
.....
Platform_STATUS platform_init(platform_init_flags * p_flags,
platform_init_config * p_config)
{
CSL_Status status;
PllcHwSetup pllc_hwSetup;
PllcHwSetup pllc_hwSetupRead;
volatile uint32_t i;
struct pll_init_data ddr_pll_data[2] =
{
{DDR3A_PLL, PLLM_DDR3A, PLLD_DDR3A, PLLOD_DDR3A},
{DDR3B_PLL, PLLM_DDR3B, PLLD_DDR3B, PLLOD_DDR3B}
};
#ifdef PLATFORM_PLL_REINIT
int loop_count;
#endif
/*************************************************************************
* This routine may be called before BIOS or the application has loaded.
* Do not try and write debug statements from here.
***********************************************************************/
if ((p_flags == 0) || (p_config == 0))
{
platform_errno = PLATFORM_ERRNO_INVALID_ARGUMENT;
return (Platform_STATUS)Platform_EFAIL;
}
/* Start TCSL so its free running */
CSL_chipWriteTSCL(0);
CSL_BootCfgUnlockKicker(); //added here and removed in DDR3Init
#ifdef PLATFORM_PLL_REINIT
for (loop_count = 0; loop_count < 10; loop_count++) {
platform_errno = 0;
#endif
/* PLLC module handle structure */
if (p_flags->pll)
.....
I use yours init ddr3 parameters:
static ddr3_emif_config ddr3_1600_64 = {
0x6200CE62, // sdcfg // DDR3, CWL 8, CASLat. 11, 8bamks, Column 10 (1024 bytes/page), 64 bit
0x16709C55, // sdtim1
0x00001D4A, // sdtim2
0x435DFF54, // sdtim3
0x553F0CFF, // sdtim4
0xF0073200, // zqcfg
0x00001869 // sdrfc
};
static ddr3_phy_config ddr3phy_1600_64 = {
0x1C000, //pllcr
(IODDRM_MASK | ZCKSEL_MASK),// pgcr1_mask
((1 << 2) | (1 << 7) | (1 << 23)), // pgcr1_val
0x42C21590, // ptr0
0xD05612C0, // ptr1
0, /* not set in gel */ // ptr2
0x0D861A80, // ptr3
0x0C827100, // ptr4
(PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK | UDIMM_MASK),// dcr_mask //added UDIMM_MASK
((1 << 10) | (1 << 27) | (1 << 29)),// dcr_val //added (1 << 29)
0xA19DBB66,// dtpr0
0x12868300,// dtpr1
0x50035200,// dtpr2
0x00001C70,// mr0
0x00000006,// mr1
0x00000018,// mr2
0x710035C7,// dtcr
0x00F07A12,// pgcr2
0x0000005D,// zq0cr1
0x0000005B,// zq1cr1
0x0000005B,// zq2cr1
0x00000033,// pir_v1
0x0000FF81 // pir_v2
};
When I run the application after a EVM board power on is possible to see the following errors
(all the accesses are done only on offset 0 using some different 64 bit patterns):
PROMPT:> ddrTest data
DDR3 Data Bus Err. @addr 0x00000000: exp. 0xFEDCBA9876543210, found 0x0000000000000000: D Bus
Check the following Chips: M12 M14 M13 M15 subtestNr 0x1
DDR3 Data Bus Err. @addr 0x00000000: exp. 0x5555555555555555, found 0x0000000000000000: D Bus
Check the following Chips: M12 M14 M13 M15 subtestNr 0x1
DDR3 Data Bus Err. @addr 0x00000000: exp. 0x3333333333333333, found 0x0000000000000000: D Bus
Check the following Chips: M12 M14 M13 M15 subtestNr 0x2
DDR3 Data Bus Err. @addr 0x00000000: exp. 0x0F0F0F0F0F0F0F0F, found 0x0000000000000000: D Bus
Check the following Chips: M12 M14 M13 M15 subtestNr 0x3
DDR3 Data Bus Err. @addr 0x00000000: exp. 0x00FF00FF00FF00FF, found 0x0000000000000000: D Bus
Check the following Chips: M12 M14 M13 M15 subtestNr 0x4
DDR3 Data Bus Err. @addr 0x00000000: exp. 0x0000FFFF0000FFFF, found 0x0000000000000000: D Bus
Check the following Chips: M12 M13 subtestNr 0x5
DDR3 Data Bus Err. @addr 0x00000000: exp. 0xFFFF0000FFFF0000, found 0x0000000000000000: D Bus
Check the following Chips: M14 M15 subtestNr 0x6
Test DDR (ddrTest): Failed, times 1
Is it possible that I had misundestud something?
Thank you for your support.
Best regards,
Dario
Tools version:
xcdtools 3.50.8.24_core
Sys Bios 7.3.1.01
pdk k2h 4.0.12
ipc 3.50.3.04
edma 2.12.5
