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Compiler/TM4C123FH6PM: new/delete is not reenterant?

Part Number: TM4C123FH6PM

Tool/software: TI C/C++ Compiler

Good day!

Developing an application for my Tiva-based design I noticed somtimes it falls to hard fault exception usually from memory allocation/dealocation routines, and I see the memory block chain is corrupt. The new/delete calls are made from both main code and ISR routines, so I see this issue appeared then interrupt occured during memory allocation/deallocation call.

Is there any reenterant version of these library? Or, maybe, can I alter (or hook) only these calls by disabling interrupts at beggining of routine and enabling it back upon return?

  • I can't give you a complete answer, but I can shed some light.  Please search the TI ARM compiler manual for the sub-chapter titled Handling Reentrancy.  And read this article on reentrancy.   I'm not aware of any examples published by TI on how to handle calling new/delete from interrupt functions.

    Thanks and regards,

    -George

  • What version of the TI ARM compiler are you using?  Please note this is not the same as the CCS version.

    Are you using C++ exceptions?

    The new/delete functionality provided by the TI ARM compiler's run-time support (RTS) library (the C library) just calls malloc/free.  The malloc/free implementation does have code to implement a critical section for reentrancy, but you need to register a lock/unlock function pair, or the critical section won't be protected.  See the section on rentrancy in the TI ARM compiler manual mentioned above by George.

    In general, you should probably avoid dynamic allocation during ISR routines to avoid reentrancy issues and to avoid dynamic allocation at unpredictable times.

  • In my opinion, I need just to insert global interrupt disable before any malloc/free call and restore global interrupt upon exit of these calls. But this approach require installing own malloc/free function, is it possible?

  • Digging through RTS code I just realized that lock/unlock mechnism is already embedded into malloc/free code, so I can register interrupt disable/enable there. Thank you.